cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 68

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Expansion Bus (EBUS)
3.1.5
3.1.6
3.1.7
3-6
Data Duration
Bus Access Interval
PCI to EBUS Interaction
The CX28560 can extend the duration that the data bits are valid for any given EBUS
data phase. This is accomplished by specifying a value from 0–7 in the ELAPSE bit
field in EBUS Configuration register. The value specifies the additional ECLK
periods the data bits remain asserted. That is, a value of 0 specifies the data remains
asserted for one ECLK period, and a value of 7 specifies the data remains asserted for
eight ECLK periods. Disabling the ECLK signal output does not affect the delay
mechanism.
A pre- and post-data cycle is always present during the data phase of an EBUS cycle.
The pre-data cycle is one ECLK period long and provides the CX28560 sufficient
setup and hold time for the data signals. The post-data cycle is one ECLK period long
and provides CX28560 sufficient time to transition between the data phase and the
following bus cycle termination. The pre- and post-cycles are not included in the data
duration.
The CX28560 can be configured to wait a specified amount of time after it releases
the EBUS and before it requests the EBUS. This is accomplished by specifying a
value from 0–7 in the BLAPSE bit field in EBUS configuration register. The value
specifies the additional ECLK periods the CX28560 waits immediately after releasing
the bus. That is, a value of 0 specifies a wait of one ECLK period, and a value of 5
specifies six ECLK periods. Disabling the ECLK signal output does not affect this
wait mechanism. The bus grant signal (HLDA/BG*) is deasserted by the bus arbiter
only after the bus request signal (HOLD/BR*) is deasserted by the CX28560. As the
amount of time between bus request deassertion and bus grant deassertion can vary
from system to system, it is possible for a misinterpretation of the old bus grant signal
as an approval to access the EBUS. The CX28560 provides the flexibility—through
the bus access interval feature—to wait a specific number of ECLK periods between
subsequent bus requests.
Refer to EBUS timing diagrams—Figure 9-8, EBUS Write/Read Cycle, Intel-Style
(Intel) and Figure 9-9, EBUS Write/Read Cycle, Motorola-Style (Motorola).
The CX28560 provides an identical EBUS interface to the CX28500 that is a
significant improvement compared to previous HDLC devices (CN8478/CN8474/
CN8472). PCI utilization is dramatically improved by enabling the EBUS accesses,
reads and writes, to be burst over the PCI bus—when EBUS is extensively used to
access EBUS peripheral during normal operation.
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B