cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 114

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5.6
5.6.1
Table 5-21. Transmit POS-PHY Thresholds Register
5.6.2
Table 5-22. Transmit POS-PHY Control Register
5-24
31:25
24:16
31:3
15:9
Bit
Bit
8:0
31
2
1
0
RSVD
TPOSBUFFFULLIEN
TPPARERRIEN
TPERRIEN
RSVD
TPTPAHITH
RSVD
TPTPALOWTH
DISBLPAR
Field Name
Field Name
POS-PHY Control Registers
Transmit POS-PHY Thresholds Register
Transmit POS-PHY Control Register
The Transmit POS-PHY Control register provides the necessary parameters for flow
control on the POS-PHY interface.
This register controls the parameter necessary to make the POS-PHY work.
Value
—
—
Value
1
0
0
0
0
0
1
0
1
0
1
Data arriving on the Transmit POS-PHY will be checked for correct parity.
Parity checking is disabled.
Transmit POS-PHY thresholds.
PTPA High Threshold.
Above this number of dwords (4 bytes) in the buffer, the bus request is deasserted.
Reserved
PTPA Low Threshold.
Below this number of dwords (4 bytes) in the buffer, the bus request is asserted.
Reserved.
POS-PHY Buffer Full Interrupt Disabled.
POS-PHY Buffer Full Interrupt Enabled.
On encountering full POS-PHY buffers, an interrupt will be generated.
POS-PHY Parity Error Interrupt Disabled.
POS-PHY Parity Error Interrupt Enabled.
On detection of a parity bit error, a parity error interrupt will be generated.
POS-PHY Error Interrupt Disabled.
POS-PHY Error Interrupt Enabled.
When the POS-PHY Error pin is asserted an interrupt will be generated.
Mindspeed Technologies™
Advance Information
Description
Description
CX28560 Data Sheet
28560-DSH-001-B