cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 23

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
1.1.1.3
28560-DSH-001-B
TSBUS—Time Slot Bus
The CX28560 provides a TSBUS interface for variable bandwidth time slots, Virtual
Serial Port (VSP). A VSP is defined as an entity—quantified by clock bus rate divided
by number of time slots—which provides multiple asynchronous paths over a single
serial port. A programmable number of VSPs per TSBUS are allowed by using the
existing start and end address time slot pointer mechanism. This mechanism allows
the CX28560 to allocate any number of VSPs on a given serial port.
The total number of time slots allocated across all ports must not exceed 8192, the
total number of logical channels must not exceed 2047, and the serial port clock speed
must not exceed 52 MHz.
While operating in TSBUS mode, the minimum number of time slots required is 5.
The programmable number of time slots, implemented by the pointer mechanism (i.e.,
configurable start and end addresses) allows any number of time slots to be
concatenated into a single logical channel. This concatenation allows mixed VTG
path options without changing the number of time slots assigned to the TSBUS port.
The stuff signal provides the CX28560 with the information necessary to pad time
slots in the transmit direction, or to ignore them in the receive.
When working in TSBUS mode, DS0 signals can be extracted from a higher level
(SONET/SDH/DS3 or E3) payload bit stream. This is performed in a similar manner
to the TSBUS frame mechanism, by using a group synchronizing pulse and a pointer
mechanism. Each group occupies fixed places in the time slot map. When this
position is reached, a group time slot map is consulted in order to retrieve the relevant
channel number. (See
Mindspeed Technologies™
Advance Information
Appendix D
for a detailed description).
Introduction
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