cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 102

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
Table 5-14. Interrupt Queue Pointer
Table 5-15. Interrupt Queue Length
5.3.1.1
5-12
31:3
31:15
Bit
2:0
14:0
Bit
Field Name
IQPTR[31:3]
IQPTR[2:0]
Field Name
IQLEN[14:0]
RSVD
Value
Value
Interrupt Descriptors
The interrupt descriptor describes the format of data transferred into the queue. There
are two different types of the interrupt descriptor. The first type is used to represent
BUFFC's block related interrupts and the second type is used to represent other
interrupts. Both types are 64-bit fields. Generically, the interrupt descriptor includes
fields for:
All the interrupts are associated with a channel or direction with the following four
exceptions:
—
0
—
0
• Identifying the source of interrupt from within the CX28560 channel causing
• Events assisting the host in synchronization channel, port and independent
• Errors and unexpected conditions resulting in lost data, discontinued message
1.
the interrupt (1-2047) and direction (receive or transmit)
activities
processing, or prevented successful completion of a service request
When an OOF or COFA condition is detected on a serial port, only one
interrupt is generated for the port until the condition is cleared and the
condition reoccurs.
Shared Memory Interrupt Queue Pointer
These 29 bits are appended with 000b to form a 64-bit aligned address. This address points
to the first entry (Quad-word) of the Interrupt Queue buffer. The host can change this field
while the chip is operating. However, this results in flushing all interrupts residing in the
internal interrupts FIFO.
Ensures 64 bit alignment
Reserved
Shared Memory Interrupt Queue Length
This 15-bit number specifies the length of the Interrupt Queue buffer in Quad-words (i.e.,
the number of descriptors in the queue).
NOTE(S):
1. The host may change this field while the chip is operating. However, this results in
flushing all interrupts residing in the internal interrupts FIFO. After reset, IQLEN is set
to 0. This has the effect of blocking all the interrupt processing by the CX28560.
Mindspeed Technologies™
Advance Information
Description
Description
CX28560 Data Sheet
28560-DSH-001-B