cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 163

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
7.2.5.3
7.2.6
7.2.6.1
7.2.6.2
7.2.7
7.2.7.1
28560-DSH-001-B
Transmit Events
Receive Events
Ending a Message with an Abort or Sending an Abort Sequence
If the abort and the EOM indications are set in a fragment header, the CX28560
interprets it as a request to end an in-progress message with the abort sequence. If the
previous fragment header contained an End-Of-Message (EOM) indication, the abort
request is ignored. If the previous fragment header was not EOM (i.e., a transmit
message was in-progress), an abort code sequence is transmitted to end that partially
sent message. Transmission of an abort code sequence is defined as 16 consecutive 1s.
Transmit events are informational in nature and do not require channel recovery actions.
End Of Message (EOM)
Reason:
Effects:
Transmit COFA Recovery (TCREC)
Reason:
Effects:
Channel-Level Recovery Actions:
Receive events are informational in nature and do not require channel recovery actions.
End Of Message (EOM)
Reason:
• TSLP has transmitted (actually, transferred to the TSIU) the last bit of a data
• TxEOM interrupt (if EOMIEN = 1 in
• TSLP and TBUFFC continue normal processing. If the TBUFFC does not
• TSIU terminates the internal COFA condition due to the arrival of a TSYNC/
• TCREC Interrupt (if COFAIEN = 1 in
• Transmit channel reactivation should be performed.
• RSLP has detected the end of a message (closing flag or an error condition).
buffer (excluding the FCS and closing flag) and the Transmit Fragment Header
signifies that the fragment contained an end of a message (EOM = 1).
Configuration register).
receive more data from the system over the POS-PHY before the TSLP needs
to output the next data bit, TSLP outputs another octet of flag or idle code.
TSTB pulse followed by at least the assigned number of time slots for this port
without another unexpected TSYNC/TSTB pulse. This interrupt will also be
generated when a suitable number of time slots have passed after a COFA
interrupt generated by the first sync pulse.
register).
Mindspeed Technologies™
Advance Information
Chapter
Chapter
5.0, TSLP Channel
5.0, TSIU Port Configuration
Basic Operations
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