cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 160

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Basic Operations
7.1.2
7.2
7-2
Receive
HDLC Mode
NOTE:
The receiver processes data from the serial interface only if all of the following
conditions are true:
If any of the first three above conditions is not true, the receiver ignores the incoming
data stream. If the last condition is not true, eventually an overflow will occur for the
channel.
Data is transferred to the system in fragments over the POS-PHY interface, prefixed
with a fragment header. The first data is sent for a channel after activation as soon as a
complete fragment has been completed.
The CX28560 supports three HDLC modes. The modes are assigned on a per-channel
and direction basis by setting the PROTOCOL bit field within the RSLP/TSLP
Channel Configuration registers. The HDLC modes are as follows:
HDLC protocol-specific support in the transmitter includes the following:
HDLC protocol-specific support in the receiver includes the following:
• RxENBL bit is set to 1 in the port’s RSIU Port Configuration register.(see
• Receive channel is mapped to time slot(s), that are enabled in the port’s RSIU
• Receive channel has been activated by a host via service request.
• The channel number appears at least once in the active Flexiframe.
• HDLC-NOCRC: HDLC support, no CRC
• HDLC-16CRC: HDLC support, 16-bit CRC
• HDLC-32CRC: HDLC support, 32-bit CRC
• Generate opening/closing/shared flags
• Zero-bit insertion after five consecutive 1s are transmitted
• Generate pad fill between frames and adjust for zero insertions
• Generate 0-, 16- or 32-bit CRC (i.e., FCS)
• Generate abort sequences upon FIFO underflow condition or as instructed on a
• Data inversion of all bits (including flags and pad fill characters)
• Detection and extraction of opening/closing/shared flags
• Detection of shared-0 between successive flags
• Zero bit extraction after five consecutive 1s are received
• Detect changes in pad fill idle codes
If TxENBL = 1 and the port is configured in any channelized mode (i.e., not
unchannelized), until the first TSYNC/TSTB pulse is detected, that port
outputs either a three-state signal or an all 1s signal, depending on the state of
the TRITx bit field.
Chapter
Time Slot Configuration register. (see
per-message basis by asserting the error line on the POS-PHY or by setting the
abort bit in the fragment header of the last fragment of the packet.
Mindspeed Technologies™
5.0)
Advance Information
Chapter
5.0)
CX28560 Data Sheet
28560-DSH-001-B