cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 101

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.3
5.3.1
28560-DSH-001-B
Interrupt Level Descriptors
Interrupt Queue Register
The CX28560 generates interrupts for a variety of reasons. Interrupts are events or
errors detected by the CX28560 during processing of the incoming serial data
streams. Interrupts are generated by the CX28560 and forwarded to the host for
servicing.
The CX28560 gathers the many events and errors (generated by all units such as
RBUFFC and TBUFFC, RSLP and TSLP, and SIU) and notifies the host over the
PCI. Interrupt Descriptors are generated by the CX28560 and forwarded to the host
for servicing. Individual types of interrupts may be masked from being generated by
setting the appropriate interrupt mask or interrupt disable bit fields in various
descriptors. The interrupt mechanism, each individual interrupt, and interrupt
controlling mechanisms are discussed in this section.
The CX28560 employs a single Interrupt Queue Register to communicate interrupt
information to the host. This register is stored within the CX28560. This register
stores the location and the size of an interrupt queue (user configurable) in allocated
shared memory where the interrupt descriptors will be directly placed by the
CX28560 while acting as a PCI bus master. The CX28560 requires this information to
transfer interrupt descriptors to shared memory. All the interrupts are processed by the
host, in an Interrupt Service Routine (ISR). The CX28560's PCI interface must be
configured to allow bus mastering.
The Interrupt Queue Register (i.e., Interrupt Queue Pointer and Interrupt Queue
Length) is initialized by the host via a direct PCI write transaction. After a PCI Reset
or Software Chip Reset (SCR), the Interrupt Queue Pointer is the first register that
needs to be initialized. A typical initialization procedure is as follows:
NOTE:
1.
2.
The host writes in the Interrupt Queue Pointer register allocated by performing
a direct write to the address of the Interrupt Queue in shared memory.
The host writes in the Interrupt Queue Length by performing a direct write to
this location, the value of the interrupt queue length allocated in shared
memory.
The user can change, at any time, the length of the Interrupt Queue (IQLEN
field in the Interrupt Queue Length register) or the pointer value of the
Interrupt Queue Pointer (IQPTR field in the Interrupt Queue Pointer register).
However, writing to these registers while the chip is operating may result in
flushing the interrupts held in the internal FIFO.
Mindspeed Technologies™
Advance Information
The CX28560 Memory Organization
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