cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 153

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
28560-DSH-001-B
6.
7.
l.
m.
n.
o.
p.
q.
r.
s.
t.
u.
v.
w.
x.
y.
z.
aa.
ab.
ac.
ad.
ae.
af.
Perform a CH_ACT Service Request and wait for SACK when the SACKIEN
bit is set.
For each channel that must be activated, the host prepares a CH_ACT Service
Request and inserts it into The Service Request table. The host may decide if to
activate all channels by writing the Service Request queries into one single
Service Request table or by splitting the service request commands into one or
more tables. For each CH_ACT Service Request the host follows the same
steps as were specified at 1–5 in this section.
RSIU Group Map [8192] (for each group time slot that is going to be used)
RSIU Time Slot/Group Map Pointer Allocation [32] (one per port)
RSIU Group Map Pointer Allocation [64] (one per group required)
RSIU Group State Register [512] (for each group, the relevant state register
should be set to zero).
RSIU Port Configuration [32] (for each port that should operate, this
command activates the port)
TSLP Channel Configuration [2047] (one for each channel that is going to
be activated)
TBUFFC Configuration [2047] (one for each channel that is going to be
activated)
TBUFFC Flexiframe Memory [1] (one per chip)
TBUFFC Data FIFO Size [1] (one per chip)
TBUFFC Fragment Size [1] (one per chip)
TBUFFC Slot Time [1] (one per chip)
TBUFFC Flexiframe Control [1] (one per chip)
TSIU Time Slot/Group Map [8192] (for each time slot that is going to be
used)
TSIU Group Map [8192] (for each group time slot that is going to be used)
TSIU Time Slot/Group Map Pointer Allocation [32] (one per port)
TSIU Group Map Pointer Allocation [64] (one per group required)
TSIU Group State Register [512] (for each group, the relevant state register
should be set to zero).
TSIU Port Configuration [32] (for each port which should operate, this
command activates the port)
Transmit POS-PHY Thresholds register [1] (once per chip)
Transmit POS-PHY Control register [1] (once per chip)
Receive POS-PHY Control register [1] (once per chip)
Mindspeed Technologies™
Advance Information
Functional Description
6
-
7