cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 30

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
1.5
Figure 1-2. System Overview
1-12
PCI Bus
Local Bus
Processor
System Overview
Host
PCI Bridge
Local Bus
CX28560 supports 32 fully independent serial ports that can be configured to run in
channelized, unchannelized, T1 or TSBUS (with or without DS0 extraction) mode.
For example, in the channelized mode, the first 12 ports can operate up to 51.81 Mbps
(STS-1 rate) while the another 20 ports can operate up to 12.96 Mbps (maximum
SONET overhead rate). Each STS-1 frame transports 28xT1, 1xT3, 21xE1 or mixed
T1/E1 VTG paths, while the overhead bit streams contain the overhead required. The
configuration is valid as long as the overall number of time slots per the whole device
is 8192 time slots or less. For other restrictions see
of the CX28560’s ports can interface unchannelized data streams (HDLC or
unformatted). In this mode, each of the first twelve ports can be configured to operate
up to 52 Mbps. The restriction is that the overall data bandwidth must not exceed 700
Mbps (full duplex). The CX28560 manages uniformly allocated buffer memory
according to the Flexiframe algorithm for each of the active data channel, allowing
the user to reconfigure any channel without affecting other active channels. The on-
device features allow data transmission between buffer memory and the serial
interfaces with minimum host processor intervention. This allows the host processor
to concentrate on managing the higher layers of the protocol stack.
Memory
Shared
Mindspeed Technologies™
Interface
Interface
JTAG
POS-
PHY
PCI
Advance Information
Optional
Components
EBUS
Processing
Interface
Blocks
EBUS
Local
Host
Interface 31
Interface 0
Interface
Serial
Serial
Serial
Unit
Section
Memory
Local
1.1.1.2. Alternatively, any
Interface 31
Interface 0
Interface 1
Physical
Physical
Physical
CX28560 Data Sheet
28560-DSH-001-B
101302_001