cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 49

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
2.1.1
2.1.1.1
2.1.1.2
28560-DSH-001-B
PCI Interface
The host interface in the CX28560 is compliant with the PCI Local Bus Specification
(Revision 2.2). The CX28560 provides a PCI interface specific to 3.3 V and 33 MHz
operation and supports as master a 32-bit bus with multiplexed address and data lines,
and as a slave, a 32-bit PCI bus.
NOTE:
PCI Initialization
Generally, when a system initializes a module containing a PCI device, the
configuration manager reads the configuration space of each PCI device on a PCI bus.
Hardware signals select a specific PCI device based on a bus number, a slot number,
and a function number. If a device that is addressed (via signal lines) responds to the
configuration cycle by claiming the bus, then that function’s configuration space is
read out from the device during the cycle. Since any PCI device can be a multi-
function device, every supported function’s configuration space needs to be read from
the device. Based on the information read, the configuration manager will assign
system resources to each supported function within the device. Sometimes new
information needs to be written into the function’s configuration space. This is
accomplished with a configuration write cycle.
The CX28560 is a single function device that has device-resident memory to store the
required configuration information. The CX28560 supports Function 0 only.
PCI Bus Operations
The CX28560 behaves either as a PCI master or a PCI slave device at any time and
switches between these modes as required during device operation. The CX28560
supports only dword write transactions.
As a PCI slave, the CX28560 responds to the following PCI bus operations:
NOTE:
As a PCI master, the CX28560 generates the following PCI bus operations:
• Memory Read
• Memory Write
• Configuration Read
• Configuration Write
• Memory Read Multiple (treated like Memory Read in slave mode)
• Memory Read Line (treated like Memory Read in slave mode)
• Memory Write and Invalidate (treated like Memory Write)
• Memory Read
• Memory Read Line
• Memory Read Multiple
• Memory Write
The PCI Local Bus Specification (Revision 2.2) is an architectural, timing,
electrical, and physical interface standard that provides a mechanism for a
device to interconnect with processor and memory systems over a standard bus.
The host interface can act as a PCI master and a PCI slave, and contains the
CX28560’s PCI configuration space and internal registers. When the CX28560
needs to access shared memory, it masters the PCI bus and completes the
memory cycles without external intervention.
As a PCI slave, the CX28560 does not support bursted read or write PCI
transactions. The CX28560 ignores all other PCI cycles.
Mindspeed Technologies™
Advance Information
Host Interfaces
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