cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 119

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.7.4
Table 5-27. RBUFFC Channel Configuration Register
28560-DSH-001-B
31:22
17:16
15:0
Bit
21
20
19
18
RSVD
REOMIEN
RERRIEN
RTOOSHIEN
RCMDCIEN
RSVD
RSTARTADD
Field Name
RBUFFC Channel Configuration Register
Value
This register controls the operation mode for a channel. It contains parameters
necessary for the division of the internal memory to channel FIFOs. There is one
Channel Configuration Register for each logical channel (i.e., 2047).
The CX28560’s internal Rx memory is a 320 KB dual RAM, which may be split to
2047 parts, one part for each channel. The allocation granularity is 8 bytes.
In the CX28560, regardless of its bit rate, each channel receives an identical
allocation of memory. The difference in bit rates is accounted for by extra servicing of
faster channels according to the Flexiframe algorithm. Hence the length of a channel’s
buffer is set once (see
specify the start address of the internal data buffer. (see
FIFO Size
NOTE:
In addition the end address of each channel must be higher than the start address – no
roll-over at the end of the data FIFO is permitted.
—
0
0
1
0
1
0
1
0
1
0
The host must set the buffers so there is no overlap between buffers belonging
to different channels. Each receive channel must be allocated buffer space
before the channel can be activated.
Reserved.
End Of Message (without errors) Interrupt Disabled.
End Of Message (without errors) Interrupt Enabled.
Any error-free message received will cause this interrupt to be generated.
End Of Errored Message Interrupt Disabled.
End Of Errored Message Interrupt Enabled.
Any message received containing any error (other than too short) will cause this interrupt
to be generated.
End Of Message with Too Short Error Interrupt Disabled.
End Of Message with Too Short Error Interrupt Enabled.
Any message containing an error for which data has not been passed to the RBUFFC will
cause a too short error interrupt to be generated.
End of Channel Command Execution Interrupt Disabled.
End of Channel Command Execution Interrupt Enabled.
On completion of command (activation or deactivation) an interrupt will be generated.
Reserved.
Channel DATA FIFO Start Pointer—in units of Qwords.
Calculation)
Mindspeed Technologies™
Advance Information
Table
5-30). However, for each active channel it is required to
Description
Appendix E:Buffer Controller
The CX28560 Memory Organization
5
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29