cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 45
cx28560
Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28560.pdf
(274 pages)
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CX28560 Data Sheet
Table 1-11. EBUS Interface (Communication with Peripheral Components)
28560-DSH-001-B
ECLK
EAD[31:0]
EBE[3:0]
ALE (AS)
WR (R/WR)
RD (DS)
HOLD (BR)
HLDA (BG*)
BGACK
Pin Name
I/O
I/O
O
O
O
O
O
O
O
I
Ref Clk
ECLK
ECLK
ECLK
ECLK
ECLK
ECLK
ECLK
ECLK
—
Mindspeed Technologies™
Expansion Bus Clock (ECLK). The ECLK bit field is an inverted version of the PCI
clock.
Expansion Bus Address and Data (EAD[31:0]). EAD[31:0] is a multiplexed
address/data bus.
Expansion Bus Byte Enables (EBE[3:0]). EBE contains byte-enabled information
for the EBUS transaction.
Address Latch Enable (ALE (AS)). High-to-low transition indicates that
EAD[31:0] bus contains valid address. Remains asserted low through the data
phase of the EBUS access. (In Motorola mode, high-to-low transition indicates
EBUS contains a valid address. Remains asserted for the entire access cycle.)
Write Strobe (WR (R/WR)). High-to-low transition enables write data from
CX28560 into peripheral device. Rising edge defines write. (In Motorola
R/WR is held high throughout read and held low throughout write. Determines
meaning of DS strobe.)
Read Strobe (RD (DS)). High-to-low transition enables read data from peripheral
into CX28560. Held high throughout write operation. (In Motorola mode, DS
transitions low for both read and write operations and is held low throughout the
operation.)
Hold Request (Bus Request) (HOLD (BR)). When asserted, CX28560 requests
control of the EBUS.
Hold Acknowledge (Bus Grant) (HLDA (BG)). When asserted, CX28560 has
access to the EBUS. It is held asserted when there are no other masters
connected to the bus, or asserted as a handshake mechanism to control EBUS
arbitration.
Bus Grant Acknowledge (BGACK). When asserted, CX28560 acknowledges to the
bus arbiter that the bus grant signal was detected and a bus cycle is sustained by
CX28560 until this signal is de-asserted.
Advance Information
Description
Introduction
.
mode,
1
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27
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