cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 251

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

E.1
E.1.1
28560-DSH-001-B
Introduction
Terminology
Appendix E: Buffer Controller FIFO
This appendix aims to prove that there exists a maximum buffer size required to
contain the information in the buffer controller, and to calculate that maximum.
The analysis is based on the Flexiframe algorithm and the CX28560 receive
buffer controller design. Fuller explanations can be found in the relevant
documentation. The proof applies to 56-byte fragments, and a minimum packet
length of 40 bytes. Extrapolation to other values for these parameters is provided
via example at the end of the analysis.
Flexiframe is the algorithm used to implement a channel service scheduler.
RSLP—Receive Serial Line Processor. Block that interfaces with the buffer
controller providing a maximum of 32 bits of data and one 8-bit message status
per system clock.
An overflow is said to have occurred when new data/status arrives from the RSLP
and there is no further space available in the FIFO.
Mindspeed Technologies™
Advance Information
Size Calculation
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