cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 43

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table 1-10. PCI Interface (1 of 2)
28560-DSH-001-B
PCLK
AD[31:0]
CBE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
DEVSEL
IDSEL
Pin Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
Ref Clk
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
—
Mindspeed Technologies™
PCI Clock (PCLK). PCLK provides timing for all PCI transitions. All PCI signals
except PRST*, INTA*, and INTB* are synchronous to PCLK and are sampled on
the rising edge of PCLK. The CX28560 supports a PCI clock up to 33 MHz.
PCI Address and Data (AD[31:0]). AD[31:0] is a multiplexed address/data bus. A
PCI transaction consists of an address phase during the first clock period
followed by one or more data phases. AD[7:0] is the LSB. As both a master and a
target, the CX28560 supports only 32-bit operations.
PCI Command and Byte Enables (CBE[3:0]). During the address phase, CBE[3:0]
contain command information. During the data phases, CBE[3:0] contain
information denoting which byte lanes are valid.
Supported PCI commands are defined as follows:
CBE[3:0]
6h 0110b
7h 0111b
Ah 1010b
Bh 1011b
Ch 1100b
Eh 1110b
Fh 1111b
PCI Parity (PAR). The number of 1s on PAR, AD[31:0], and CBE[3:0] is an even
number. PAR always lags AD[31:0] and CBE* by one clock. During address
phases, PAR is stable and valid one clock after the address; during the data
phases, it is stable and valid one clock after TRDY on reads and one clock after
IRDY on writes. It remains valid until one clock after the completion of the data
phase.
PCI Frame (FRAME). FRAME is driven by the current master to indicate the
beginning and duration of a bus cycle. Data cycles continue as FRAME stays
asserted. The final data cycle is indicated by the deassertion of FRAME. For a
non-burst, one-data-cycle bus cycle, this pin is only asserted for the address
phase.
PCI Target Ready (TRDY). Asserted indicates the target’s readiness to complete
the current data phase.
PCI Initiator Ready (IRDY). Asserted indicates the current master’s readiness to
complete the current data phase.
PCI Stop (STOP). Asserted indicates the selected target is requesting the master
to stop the current transaction.
PCI Device Select (DEVSEL). Asserted indicates that the driving device has
decoded its address as the target of the current cycle.
PCI Initialization Device Select (IDSEL). This input is used to select the CX28560
as the target for configuration read or write cycles.
Advance Information
Command Type
Memory Read
Memory Write
Configuration Read (target only)
Configuration Write (target only)
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate (target only)
Description
Introduction
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