cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 38

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
Table 1-6. Serial Interface (General) (3 of 3)
1-20
RSYNC[31:0]/
RSTUFF[31:0]
RDAT[31:0]
Note(s):
1. While operating in TSBUS mode, there is no damage expected when sampling TSTBx twice, because the RCLKx and TCLKx are
2. This signal is used either as Receiver Out-Of-Frame or a Transmit Clear to Send or a TSBUS strobe. (OOF/FREC behavior
3. If the serial port operates in conventional mode, this signal is used either as a ROOFx or CTSx signal.
4. If the port operates in DS0 extraction mode, the signal is used as the TSBUS strobe signal, which indicates the beginning of the
5. Only one pin in the device defines all these functions.
Pin Name
the same signals for a specific port. However, this may require some additional restrictions for the board designers when these
clocks are routed.
selected by OOFABT = 1, CTS behavior selected by CTSENB = 1, TSTB behavior selected by TPORT_TYPE or RPORT_TYPE).
TSBUS frame.
I/O
I
I
RCLK[31:0]
RCLK[31:0]
Ref Clk
Receive Synchronization/Receive Stuff (RSYNC[31:0]/ RSTUFF[31:0]). If the port
operates in a conventional mode, this signal is defined as RSYNC. RSYNC is sampled
on the configured active edge of the corresponding receive clock, RCLKx. RSYNCx is
ignored if the serial port is configured to operate in unchannelized mode.
If RSYNCx signal transitions from low to high, the start of a receive frame is indicated.
For T1 mode, the corresponding sampled and stored data bit during the same bit-time
period (not necessarily sampled on the same clock edge) is the F-bit. For the
conventional channelized mode, the corresponding data bit sampled and stored during
the same bit time period (not necessarily sampled on the same clock edge) is bit 0 of
the first time slot of the N.... 64 frame.
RSYNCx must remain asserted high for a minimum of PCI setup and hold time relative
to the active clock edge of this signal. Since the CX28560’s flywheel mechanism is
always used in channelized mode, no other synchronization signal is required to track
the start of each subsequent frame.
If the port operates as a TSBUS port, this signal is RSTUFF. The RSTUFF is sampled on
the configured active edge of the corresponding RCLKx. In this case, RSTUFF assertion
indicates that this time slot contains no data.
While operating in channelized mode, the CX28560 expects assertion of this signal
within the first two bits of the time slot. Assertion of this signal elsewhere in the time
slot might result in undefined behavior.
Receive Data (RDAT[31:0]) Serial data sampled on active edge of receive clock, RCLKx.
If the channel is mapped to a time slot, input bit is sampled and transferred to memory.
If the channel is unmapped to time slot, data bit is considered invalid and the CX28560
ignores the received sample.
Mindspeed Technologies™
Advance Information
Description
CX28560 Data Sheet
28560-DSH-001-B