cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 180
cx28560
Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28560.pdf
(274 pages)
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Electrical and Mechanical Specification
Table 8-5. PCI Clock (PCLK) Waveform Parameters, 3.3 V Clock
Table 8-6. PCI Reset Parameters
8-4
T
T
T
V
NOTE(S):
(1)
(2)
T
T
T
cyc
rst
rst_clk
rst-off
high
low
ptp
CX28560 works with any clock frequency between DC and 33 MHz, nominally. The clock frequency may be changed at any
time during operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times are
not violated. The clock may only be stopped in a low state.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.
Symbol
Symbol
—
Reset Active Time after Power Stable
Reset Active Time after Clock Stable
Reset Active to Float Delay
Clock Cycle Time
Clock High Time
Clock Low Time
Clock Slew Rate
Peak-to-Peak Voltage
Figure 8-1. PCI Clock (PCLK) Waveform, 3.3 V Clock
0.3
0.4
V
0.5
Parameter
cc
(2)
(1)
V
cc
V
cc
Mindspeed Technologies™
Parameter
Advance Information
0.6
T
high
V
cc
33 MHz
0.4 V
T
Min
cyc
30
11
11
1
cc
Min
100
—
1
0.2
T
low
V
33 MHz
Infinite
cc
Max
—
—
—
4
Max
—
—
40
CX28560 Data Sheet
28560-DSH-001-B
Units
V/ns
Units
ns
ns
ns
(min)
V
ms
V
µs
ns
500031A_001
ptp
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