cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 56

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Host Interfaces
2.2.1.3
Table 2-4. Register 2, Address 08h
2.2.1.4
Table 2-5. Register 3, Address 0Ch
2-10
Bit Field
Bit Field
31:24
23:16
31:24
23:16
15:11
15:8
10:8
7:0
7:0
Class Code
Sub Class Code
Register Level
Programming
Interface
Revision Id
Reserved
Header Type
Latency Timer
—
Reserved
Name
Name
Register 2, Address 08h
This location contains the Class Code and Revision ID registers. The Class Code
register contains the Base Code, Sub Class, and Register Level Programming
Interface fields. These are used to specify the generic function of the CX28560. The
Revision ID register denotes the version of the device.
Register 3, Address 0Ch
Reset
Value
Reset
Value
02h
80h
00h
0
0
0
0
0
0
Type
Type
Mindspeed Technologies™
RO
RO
RO
RO
RW
RO
RO
RO
RO
Function: Network Controller
Type: Other
Indicates that there is nothing special about programming the CX28560.
Denotes the revision number of the CX28560. This revision Id is divided into
two 4 bit fields. Upper nibble indicates Die ID which started from 0 for this
device. The lower nibble is used for rev number, Rev A = 0, Rev B = 1, etc.
Unused
The CX28560 is a single function device with the standard layout of
configuration register space.
The latency timer is an 8-bit value that specifies the maximum number of
PCI clocks that the CX28560 can keep the bus after starting the access cycle
by asserting its FRAME*. The latency timer ensures that the CX28560 has a
minimum time slot for it to own the bus, but places an upper limit on how
long it owns the bus.
Unused
Advance Information
Description
Description
—
CX28560 Data Sheet
28560-DSH-001-B