cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 189

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
8.2.5
Figure 8-9. EBUS Write/Read Cycle, Intel-Style
28560-DSH-001-B
NOTE(S):
1. HLDA assertion depends on the external bus arbiter. While HOLD and HLDA are both deasserted, CX28560 places shared
2. One ECLK cycle after HLDA assertion, CX28560 outputs valid command bus signals: EBE, ALE, RD*, and WR*.
3. Two ECLK cycles after HLDA assertion, CX28560 outputs valid EAD address signals.
4. ALE assertion occurs 3 ECLK cycles after HOLD and HLDA are both asserted. ALAPSE inserts a variable number of ECLK
5. EAD address remains valid for one ECLK cycle after ALE falling edge. During a write transaction, CX28560 outputs valid
6. ELAPSE inserts a variable number of ECLK cycles to extend RD*/WR* low pulse width and EAD data intervals. Read data
7. EAD write data and EBE byte enables remain valid for one ECLK cycle after RD*/WR* deassertion.
8. One ECLK after RD* or WR* deassertion, HOLD is deasserted and the bus is parked (command bus deasserted, EAD three-
9. Command bus is unparked (three-stated) one ECLK after HLDA deassertion; two different unpark phases are shown,
10. BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus request.
EBUS signals in high impedance (three-state, shown as dashed lines).
cycles to extend ALE high pulse width and EAD address interval.
EAD write data one ECLK prior to WR* assertion. During a read transaction, EAD data lines are inputs.
inputs are sampled on ECLK rising edge coincident with RD* deassertion.
state). The bus parked state ends when HLDA is deasserted.
indicating the dependence on HLDA deassertion. If HLDA remained asserted until the next bus request, then command bus
remains parked until one ECLK cycle following the next HOLD assertion. Caution: Whenever HLDA is deasserted, all shared
EBUS signals are forced to three-state after one ECLK cycle, regardless of whether the EBUS transaction was completed.
CX28560 does not reissue or repeat such an aborted transaction.
See Notes
WR*(write)
WR*(read)
EAD[31:D]
RD*(write)
RD*(read)
EBE[3:0]
EBUS Arbitration Timing Specification
HOLD
ECLK
HLDA
ALE
1
Mindspeed Technologies™
2
Byte Enables from PCI Data Phase
Advance Information
3
ALAPSE - 0
Address
5
ELAPSE - 0
Data
6
7
8
Electrical and Mechanical Specification
BLAPSE - 0
9
10
8
-
13