cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 165

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
7.2.7.6
7.2.8
7.2.8.1
7.2.8.2
28560-DSH-001-B
Transmit Errors
Receive COFA Recovery (RCREC)
Reason:
Effects:
Transmit errors are service-affecting and require a corrective action by a controlling
device (i.e., the host) to resume normal channel processing.
Transmit Underrun (BUFF)
The CX28560 needs to send more data towards the TSIU for an in-progress transmit
message, but the internal channel FIFO is empty.
Reasons:
Effects:
Channel-Level Recovery Actions:
Transmit Change Of Frame Alignment (COFA)
TSYNC or TSTB input signal transitions from low to high, but at an unexpected time
in comparison to the internal frame synchronization flywheel mechanism. COFA
errors are only applicable to channelized ports (i.e., unchannelized ports ignore the
TSYNC input). Frame synchronization indicates the expected location of the first bit
of time slot 0 on the transmit serial data output. Lacking frame synchronization, the
transmitter cannot map or align time slots. This error affects all active channels on the
respective port. Note that a similar error in TSBUS mode within the group map will
not cause an interrupt to be generated.
Reason:
• RSIU terminates the internal COFA condition due to the arrival of a RSYNC/
• RCREC Interrupt (if COFAIEN = 1 in
• RSLP and RBUFFC continue normal processing.
• Degradation of the host subsystem or application software.
• Host applied back-pressure on the Flow Conductor POS-PHY bus causing
• TxBUFF Interrupt (if BUFFIEN = 1 in
• Transmit channel enters deactivate state where the TSLP transmits a repetitive
• Transmit output is three-stated.
• Transmit channel reactivation is required.
• Signal failure, glitch or realignment caused by the physical interface sourcing
TSTB pulse followed by at least the assigned number of time slots for this port
without another unexpected RSYNC/TSTB pulse. This interrupt is also
generated after the COFA caused by the first sync pulse received on a port.
register).
reports of buffer levels not to reach the host.
Configuration register).
abort sequence of 16 consecutive 1s.
the TSYNC/TSTB input signal.
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Advance Information
Chapter
Chapter
5.0, RSIU Port Configuration
5.0, TSLP Channel
Basic Operations
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