cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 167

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
7.2.9.2
28560-DSH-001-B
Effects:
Channel-Level Recovery Actions:
Notice that channel reactivation is not required.
Receive Change Of Frame Alignment (COFA)
RSYNC or TSTB input signal transitions from low to high, but at an unexpected time
compared to the frame synchronization flywheel mechanism. COFA errors are only
applicable to channelized ports (i.e., unchannelized ports ignore the RSYNC/TSTB
input). Frame synchronization indicates the expected location of the first bit of time
slot 0 on the receive serial data input. Lacking frame synchronization, the receiver
cannot map or align time slots. This error affects all active channels on the respective
port, but does not require a host recovery action. Note that a similar error in TSBUS
mode within the group map will not cause an interrupt to be generated.
Reason:
Effects:
• RxBUFF Interrupt (if BUFFIEN = 1 in
• If a receive message was in progress, that message is marked as errored with an
• When the in-progress message reaches the top of the internal FIFO, the entire
• RxERR interrupt is generated, if ERRIEN is set in
• RBUFFC is not affected and continues to transfer data for this channel to the
• If possible, increase internal FIFO size assigned to this channel. For this action,
• Signal failure, glitch, or realignment caused by the physical interface sourcing
• First Sync to arrive at a port (this COFA interrupt should be treated as a report
• Causes serial interface to enter COFA condition until the RSYNC/TSTB pulse
• If a receive message was in-progress, that message is marked as errored. RSLP
• When the in-progress message reaches the top of the internal FIFO, the entire
Configuration register).
overflow error code. The RSLP scans for the opening flag of the next HDLC
message and any subsequent receive messages are discarded until the internal
FIFO has room to accept more RSIU data. Notice the channel remains active
and channel recovery is automatic.
HDLC message (before the overflow occurred) is transmitted to the host. In the
last fragment the status will be set as follows: EOM = 1, ERROR = BUFF.
Configuration register and
indicating a RxBUFF error overflow.
system.
all channels must first be deactivated.
the RSYNC or TSTB input signal.
of an event rather than as an error).
is followed by at least the assigned number of time slots for this port, without
another unexpected RSYNC/TSTB pulse.
scans for the opening flag of the next HDLC message and any subsequent
receive messages are discarded until the internal COFA condition has ended.
HDLC message is copied to shared memory buffers and Receive Buffer Status
Descriptors are written with ONR = HOST and ERROR = COFA (if
Mindspeed Technologies™
Advance Information
Chapter
5.0, TBUFFC Configuration register,
Chapter
5.0, RSLP Channel
Chapter
5.0, RBUFFC
Basic Operations
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