cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 61

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
2.3.1.3
2.3.1.4
2.3.1.5
28560-DSH-001-B
POS-PHY Flow Conductor Interface
The POS-PHY Flow Conductor bus implemented in the CX28560 is compliant to the
ATM POS-PHY level 3 standard (AF-PHY-0143.000) and supports other industry
standards for level 3 packet functionality at 100 MHz clock, and 8 bit wide data bus
for the transferal of report packets. This interface is identical to the receive side data
interface provided.
The Flow Conductor POS-PHY and the Receive data POS-PHY interfaces are not
fully compatible with the POS-PHY standard. Not during data transmission, if
FRENB/RENB is high (not enabled), the other signals change their value on the
following clock. During data transmission if FRENB/RENB is high, the CX28560
POS-PHY interface stores the old values on the next clock. Hence, the system should
sample data only if FRENB/RENB is low on the previous clock.
NOTE:
Receive POS-PHY Initialization
No initialization of the POS-PHY is necessary.
Transmit POS-PHY Initialization
To initialize the Transmit POS-PHY, the flow control thresholds should be set (see
above) in the data bus. No initialization is necessary for the Flow Conductor bus.
The CX28560 will always introduce a minimum of a 2 cycle delay between
packets over the POS-PHY interface.
Mindspeed Technologies™
Advance Information
Host Interfaces
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