cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 65

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
3.1
3.1.1
Table 3-1. EBUS Service Request Descriptor
28560-DSH-001-B
FOOTNOTE:
(1)
(2)
Number
dword 0
dword 1
dword 2
dword 3
Dword
All reserved bits must be written with 0s for forward compatibility.
The two LSBs must be equal to zero for dword alignment.
OPCODE[31:27]
Bit 31
EBUS—Operational Mode
Initialization
After reset and after the PCI configuration is completed, the CX28560 provides the
host the ability to read and write peripheral devices located on the EBUS
(see
CX28560 to perform specific EBUS operations. The CX28560 can perform bulk
service request commands. The Service Request Acknowledge (SACK) can be
generated either after each service request command or at the end of each bulk service
request, depending on the value of SACKIEN bit field set in the service request
configuration descriptor (see
the
entry in the Host Descriptor table. Once configured and enabled, the host can
configure local devices connected to the EBUS by issuing the EBUS Access Service
Request (EBUS_WR or EBUS_RD). The command is a three dword memory location
that contains the following dword fields:
• Access Control Field
• Shared Memory Pointer (Buffer Address) representing the starting address of
• EBUS Base Address Offset (the address of the first EBUS transaction)
Table 5-4, Service Request Pointer Register
SACKIEN[26]
Table
the buffer location where the device structure resides
3-1). The Host Service Request mechanism allows the host to instruct the
Mindspeed Technologies™
Reserved[25:19]
Advance Information
Shared Memory Pointer[31:2]
EBUS Base Address Offset
Table
Reserved
3-2). The CX28560 processes an SRQ by reading
FIFO_BURST[18]
(1)
which contains the address of the first
(2)
EBUS Byte Enable
[17:14]
Expansion Bus (EBUS)
Length[13:0]
Bit 0
3
-
3