cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 112

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5.4
Table 5-19. Global Configuration Register
5-22
NOTE(S):
1. After reset, the value of Global Configuration register is 0.
31:14
Bit
9:1
13
12
11
10
0
RSVD
POS-PHY_REG
RSVD
PCI_TARGET_FBTB
PCI_BR
RSVD
PCI_EN
Field Name
Global Configuration Register
The Global Configuration register specifies configuration information applying to the
entire device. This register must be programmed before any channel is activated. The
only field in this register that can be changed while the chip is operating (i.e., not
immediately after reset) is the PCI_EN field.
The components and their descriptors are given in
Value
0
0
1
0
0
1
1
0
0
1
0
Reserved
POS-PHY Non-Registered Mode (normal mode).
The RxENB/FRENB signal will be sampled according to the POS-PHY standard.
POS-PHY Registered Mode.
The RxENB/FRENB signal will be sampled one clock cycle later than defined in the
POS-PHY standard.
Reserved
Use the fast back-to-back feature as configured in the PCI configuration settings.
The CX28560 as PCI master attempts to fast-back-to-back the PCI transaction to
other targets regardless of PCI configuration settings. This bit is defined to force the
CX28560’s fast back-to-back capability regardless of the PCI configuration. The PCI
specification states that if there is a single device in the system that does not support
a fast back-to-back transaction as a target, the fast back-to-back mode is disabled.
Setting this bit to 1 instructs the CX28560 to ignore the PCI configuration settings
and execute fast back-to-back transactions when appropriate according to the PCI
Specification. The host can set this bit only if the CX28560 is always accessing the
same target which is capable of fast back to back transactions. This is not a violation
of the PCI specification, rather it is an implementation of an allowed behavior.
Little-Endian Storage Convention (Intel-style).
The least significant byte to be stored in and retrieved from the lowest memory
address.
Big-Endian Storage Convention (Motorola-style).
An example of little-big Endian byte ordering is shown in Appendix E.
Reserved
PCI Interrupt disabled—global interrupt mask.
PCI Interrupt enabled
Mindspeed Technologies™
Advance Information
Description
Table
5-19.
CX28560 Data Sheet
28560-DSH-001-B