cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 121

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.7.7
Table 5-30. RBUFFC Data FIFO Size Register
5.7.8
Table 5-31. RBUFFC Fragment Size Register
5.7.9
Table 5-32. RBUFFC Flexiframe Slot Time Register
28560-DSH-001-B
31:14
13:0
31:8
31:8
Bit
Bit
7:0
Bit
7:0
RSVD
RDFIFOSIZE
RSVD
RNUMWORDSFRAG
RSVD
RNUMCYCLESLOT
Field Name
Field Name
Field Name
This register defines the size of each channel’s data FIFO in 8-byte granularity. This size is fixed
once for the receive direction since all the channels are allocated the same amount of buffer
memory regardless of their bit rate. The size of the buffer should be allocated as a multiple of 8,
minimum 160 bytes per channel and maximum 32 KB (see
This fixes the maximum number of words of payload (i.e., packet data, not fragment header) that
will be transferred to the system over the POS-PHY data interface in the interval fixed by
Table
Number of Cycles per Slot – determines the number of cycles per slot and as consequence the
timing of the write transaction of a fragment towards the POS-PHY.
5-32. For the calculation to determine the relevant Fragment Size (see
RBUFFC DATA FIFO Size Register
RBUFFC Fragment Size Register
RBUFFC Flexiframe Slot Time Register
Value
—
0
0
Value
Value
—
0
—
0
Reserved.
Data FIFO Size (per channel) in DWords. The value in this register applies to all the channels.
The value in this field must be even.
Reserved.
Minimum number of cycles allocated per Flexiframe slot. This count is zero based, all
values are supported. If this is larger than three plus the number of Dwords ready to be
sent to the system, a gap will be created between fragments. The aim of this is to allow
the system to fix the amount of time it needs to perform regular (and irregular)
activities.
When configured to 0, the RBUFFC will work “as fast as possible”—the minimum
number of cycles possible (4) will be spent servicing empty slots.
Reserved.
Maximum number of words of data allocated to a fragment. The minimum
programmable value is 8 Dwords, and the maximum 64 Dwords. The register is based
on a one-based count. The length of the fragment is fixed once for the receive
direction.
Mindspeed Technologies™
Advance Information
Description
Description
Description
Appendix
E).
The CX28560 Memory Organization
Appendix
E).
5
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