cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 157

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
6.3
6.3.1
6.3.2
6.3.3
28560-DSH-001-B
Port Operations
Unmapped Time Slots
Enabling a Port
Disabling a Port
The host can stop the CX28560 from processing certain time slots regardless of the
channel activation/deactivation/ reactivation commands. This can be performed by
programming time slots in RSIU Time Slot Configuration and TSIU Time Slot
Configuration to indicate that the specific time slots are not mapped. (See
RTS_ENABLE and TTS_ENABLE bit fields in
Configuration register and TSIU Time Slot Configuration register, respectively).
NOTE:
The procedure required for enabling a receive port and a transmit port is identical.
A port can be enabled by writing a 1 to the ENBL bit in the SIU Port Configuration
register. Once a port has been enabled, changing the time slot map allocation to the
port (i.e., the STARTAD_TS and ENDAD_TS fields) is not allowed; however,
changing the mapping of the time slots to channels is allowed The new port
configuration is written to the SIU Port Configuration register.
When a port is configured to work in TSBUS mode and DS0 extraction is configured
within the port (i.e., that the groups of channels have been assigned to one or more
time slots by a group number), a special procedure is required. Before enabling the
port, the group state machines of the groups included in the port must be reset.
Resetting the group state machines is done by writing the value 0 to all 32 bits in the
Group State register (see
be enabled.
The procedure required for disabling a receive port and a transmit port is identical.
A port can be disabled by writing a 0 to the ENBL bit in the SIU Port Configuration
register. Once a port has been disabled, changing the time slot map allocation to the
port (i.e., the STARTAD_TS and ENDAD_TS fields) is allowed.
The TDAT signal is either set to logic 1 or three-state according to bit TRITx
in
Chapter
Mindspeed Technologies™
5.0, TSIU Time Slot Configuration register.
Advance Information
Chapter
5.0, RSIU and TSIU) for each group in each port to
Chapter
5.0, RSIU Time Slot
Functional Description
6
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