cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 113

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.5
Table 5-20. EBUS Configuration Register
28560-DSH-001-B
NOTE(S):
(1)
31:13
10:8
Bit
7:4
3:0
12
11
After reset, the value of EBUS Configuration register is 0.
RSVD
MPUSEL
ECKEN
ALAPSE[2:0]
BLAPSE[3:0]
ELAPSE[3:0]
Field Name
EBUS Configuration Register
Value
The EBUS Configuration Descriptor, defined in
configuration parameters for EBUS transactions. The host must configure this register
before any attempt to access the EBUS.
—
—
—
0
0
1
0
1
Reserved.
Expansion Bus Microprocessor Selection Motorola-style.
Expansion bus supports the Motorola-style microprocessor interface and uses Motorola
signals: Bus Request (BR*), Bus Grant (BG*), Address Strobe (AS*), Read/Write (R/WR*),
and Data Strobe (DS*).
Expansion Bus Microprocessor Selection– Intel-style.
Expansion bus supports the Intel-style microprocessor interface and uses Intel signals: Hold
Request (HOLD), Hold Acknowledge (HLDA), Address Latch Enable (ALE*), Write Strobe
(WR*), and Read Strobe (RD*).
Expansion Bus Clock Disabled.
ECLK output is three-stated.
Expansion Bus Clock Enabled.
The CX28560 re-drives and inverts PCLK input onto ECLK output pin.
Expansion Bus Address Duration.
The CX28560 extends the duration of valid address bits during an EBUS address phase to
ALAPSE+1 number of ECLK periods. The control lines ALE* (Intel) or AS* (Motorola)
indicate that the address bits have had the desired set-up time.
Expansion Bus Access Interval.
The CX28560 waits BLAPSE number of ECLK periods immediately after relinquishing the
bus. This wait ensures that all the bus grant signals driven by the bus arbiter have sufficient
time to be de-asserted as a result of bus request signals being de-asserted by the CX28560.
Expansion Bus Data Duration.
The CX28560 extends the duration of valid data bits during an EBUS data phase to
ELAPSE + 1 number of ECLK periods. The control lines RD* and WR* (Intel) or DS* and R/
WR* (Motorola) indicate the data bits have had the desired setup time.
Mindspeed Technologies™
Advance Information
Description
Table
5-20, specifies the
The CX28560 Memory Organization
5
-
23