cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 149

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
6.1.2
6.1.2.1
6.1.2.2
28560-DSH-001-B
Configuration
A sequence of hierarchical initialization must occur after resets. The levels of
hierarchy are as follows:
Channel and port configuration involves programming many registers and must be
done to comply with its own hierarchy, as explained below.
PCI Configuration
After power-up or a PCI reset sequence, the CX28560 enters a holding pattern. It
waits for PCI configuration cycles directed specifically for the CX28560. They are
actually directed at the PCI bus and PCI slot where the CX28560 resides.
PCI configuration involves PCI read and write cycles. These cycles are initiated by
the host and performed by a host-bus-to-PCI-bus bridge device. The cycles are
executed at the hardware signal level by the bridge device. The bridge device polls all
possible slots on the bus it controls for a PCI device, and then iteratively reads the
configuration space for all supported functions on each device. All information from
the basic configuration sequence is forwarded to the system controller or host
processor controlling the bridge device. During PCI configuration, the host can
perform the following configuration for the CX28560:
Service Request Mechanism
After PCI configuration is complete, a set of hierarchical configuration sequences
must be executed to begin operation at the channel level. The Service Request
mechanism is the main communication channel between the CX28560 and the host. It
is used to configure the CX28560’s registers, read status registers, execute
transactions over the EBUS, and activate ports and channels. The mechanism is fully
described in
• PCI Configuration—only after hardware reset
• Interrupt Queue Configuration
• Global Configuration
• POS-PHY Configuration
• Channel and Port Configuration
• Read PCI configuration space (Device Identification, Vendor Identification,
• Allocate 1 MB system memory range and assign the Base Address register
• Allow fast back-to-back transactions
• Enable PCI system error signal line, SERR*
• Allow response for PCI parity error detection
• Allow PCI bus-master mode
• Allow PCI bus-slave mode
• Assign latency
• Assign interrupt line routing
Class Code, and Revision Identification)
using this memory range
Section
Mindspeed Technologies™
5.2.1.
Advance Information
Functional Description
6
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