cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 100

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5.2.2
Table 5-12. Receive Port Alive Register
Table 5-13. Transmit Port Alive Register
5.2.3
5-10
31:0
31:0
Bit
Bit
TPA[31:0]
RPA[31:0]
Field Name
Field Name
Port Alive Registers
Soft Chip Reset Register
Value
Value
The Receive and Transmit Port Alive registers are read-only registers. These registers
can only be accessed via direct PCI transaction. Each bit of the Receive and Transmit
Port Alive register represents the device port number. Refer to
Table 5-13
—
—
These registers operate as a gate which enables or disables the access to the Port
Configuration register. If the corresponding bit of the Receive and Transmit Port
Alive register is set, a new port configuration for the specified port is allowed.
After a PCI reset or Software Chip reset, all 32 bits of the Receive and Transmit Port
Alive register are cleared (set to 0). Each bit is automatically set to 1 after 24
clock cycles occur on that specific port. After the corresponding bit is set to 1, the host
can write to the Port Configuration register. The host cannot program a new port
configuration until the corresponding bit/port is set to 1 in the Port Alive register
depending upon the direction of receive or transmit.
A proper configuration sequence for accessing the Port Configuration register is as
follows:
NOTE:
This register contains 1 bit. Any write of any value to a Soft Chip Reset (SCR) generates
a soft reset for the CX28560. An SCR affects the CX28560 exactly as PCI Reset, except
that the PCI block is not reset. No PCI configuration is performed after a SCR.
1.
2.
3.
4.
Host polls the Port Alive register for the specific port/direction and waits (24–
32 serial clock cycles) until the corresponding bit in the Port Alive register is
set (the polled bit is one).
Host issues a Service Request (SRQ) Port Configuration command and waits
for a Service Request Acknowledge (SACK).
Host gets the SACK.
Writing to the Port Configuration register causes the corresponding bit from the
Port Alive register to be cleared. This bit is automatically set to 1 after 24
serial clock cycles occur; therefore, a new port configuration will be allowed.
Host checks if a new port configuration is allowed by checking the
corresponding bit in the Port Alive register. Go to 1.
Type
Type
RO
RO
for these registers.
Mindspeed Technologies™
the 32 bits is set, then the Receive Port Configuration for that specific port is allowed.
This register controls the access to the Transmit Port Configuration register. If one
of the 32 bits is set, then the Transmit Port Configuration for that specific port is
allowed.
This register controls the access to the Receive Port Configuration register. If one of
Advance Information
Description
Description
Table 5-12
CX28560 Data Sheet
28560-DSH-001-B
and
–
32 serial
–
32