adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 9

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
Source
DMA20 IRQ (SPORT3 RX)
DMA21 IRQ (SPORT3 TX)
DMA13 IRQ (EPPI1)
DMA14 IRQ (EPPI2, Host DMA)
DMA5 IRQ (SPI1)
DMA23 IRQ (SPI2)
DMA8 IRQ (UART1 RX)
DMA9 IRQ (UART1 TX)
DMA10 IRQ (ATAPI RX)
DMA11 IRQ (ATAPI TX)
TWI0 IRQ
TWI1 IRQ
CAN0 Receive IRQ
CAN0 Transmit IRQ
MDMA Stream 2 IRQ
MDMA Stream 3 IRQ
MXVR Status IRQ
MXVR Control Message IRQ
MXVR Asynchronous Packet IRQ
EPPI1 Error IRQ
EPPI2 Error IRQ
UART3 Status IRQ
Host DMA Status
Reserved
Pixel Compositor (PIXC) Status IRQ
NFC Status IRQ
ATAPI Status IRQ
CAN1 Status IRQ
DMAR0 Block IRQ
DMAR1 Block IRQ
DMAR0 Overflow Error IRQ
DMAR1 Overflow Error IRQ
DMA15 IRQ (PIXC IN0)
DMA16 IRQ (PIXC IN1)
DMA17 IRQ (PIXC OUT)
DMA22 IRQ (SDH/NFC)
Counter (CNT) IRQ
Keypad (KEY) IRQ
CAN1 RX IRQ
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
IRQ
35
36
37
39
43
59
62
63
63
70
ID
38
40
41
42
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
61
63
63
64
65
66
67
68
69
(at Reset)
GP IRQ
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG13
IVG13
IVG11
IVG11
IVG11
IVG11
IVG9
IVG9
IVG9
IVG9
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
Rev. A | Page 9 of 88 | October 2008
IRQ ID
Core
2
2
2
2
3
3
3
3
3
3
4
4
4
4
6
6
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
Table 4. System Interrupt Controller (SIC) (Continued)
Event Control
The ADSP-BF54x Blackfin processors provide the user with a
very flexible mechanism to control the processing of events. In
the CEC, three registers are used to coordinate and control
events. Each register is 16 bits wide:
Peripheral IRQ
Source
CAN1 TX IRQ
SDH Mask 0 IRQ
SDH Mask 1 IRQ
Reserved
USB_INT0 IRQ
USB_INT1 IRQ
USB_INT2 IRQ
USB_DMAINT IRQ
OTPSEC IRQ
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 0 IRQ
Timer 1 IRQ
Timer 2 IRQ
Timer 3 IRQ
Timer 4 IRQ
Timer 5 IRQ
Timer 6 IRQ
Timer 7 IRQ
Pin IRQ 2 (PINT2)
Pin IRQ 3 (PINT3)
• CEC interrupt latch register (ILAT). The ILAT register
• CEC interrupt mask register (IMASK). The IMASK regis-
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and is processed by the CEC when asserted. A
cleared bit in the IMASK register masks the event, prevent-
ing the processor from servicing the event even though the
IRQ
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
ID
(at Reset)
GP IRQ
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IRQ ID
Core
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5