adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 2

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TABLE OF CONTENTS
General Description ................................................. 3
Pin Descriptions .................................................... 25
REVISION HISTORY
10/08—Rev. 0 to Rev. A
Delete features not currently available.
Low Power Architecture ......................................... 4
System Integration ................................................ 4
Blackfin Processor Peripherals ................................. 4
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 6
DMA Controllers ................................................ 10
Real-Time Clock ................................................. 11
Watchdog Timer ................................................ 11
Timers ............................................................. 12
Up/Down Counter and Thumbwheel Interface .......... 12
Serial Ports (SPORTs) .......................................... 12
Serial Peripheral Interface (SPI) Ports ...................... 12
UART Ports (UARTs) .......................................... 13
Controller Area Network (CAN) ............................ 13
TWI Controller Interface ...................................... 13
Ports ................................................................ 14
Pixel Compositor (PIXC) ...................................... 14
Enhanced Parallel Peripheral Interface (EPPI) ........... 14
USB On-the-Go Dual-Role Device Controller ............ 14
ATA/ATAPI–6 Interface ...................................... 15
Keypad Interface ................................................. 15
Secure Digital (SD)/SDIO Controller ....................... 15
Code Security .................................................... 15
Media Transceiver MAC Layer (MXVR) .................. 15
Dynamic Power Management ................................ 16
Voltage Regulation .............................................. 17
Clock Signals ..................................................... 18
Booting Modes ................................................... 19
Instruction Set Description ................................... 22
Development Tools ............................................. 22
Designing an Emulator-Compatible Processor Board .. 22
MXVR Board Layout Guidelines ............................ 23
Lockbox Secure Technology Disclaimer ................... 24
Rev. A | Page 2 of 88 | October 2008
Specifications ........................................................ 34
400-Ball CSP_BGA Package ...................................... 79
Outline Dimensions ................................................ 86
Ordering Guide ..................................................... 87
Operating Conditions ........................................... 34
Electrical Characteristics ....................................... 36
Absolute Maximum Ratings ................................... 39
Package Information ............................................ 39
Timing Specifications ........................................... 40
Output Drive Currents ......................................... 73
Thermal Characteristics ........................................ 78
Clock and Reset Timing ..................................... 40
Asynchronous Memory Read Cycle Timing ............ 42
Asynchronous Memory Write Cycle Timing ........... 44
DDR1 SDRAM Read Cycle Timing ....................... 46
DDR1 SDRAM Write Cycle Timing ...................... 47
External Port Bus Request and Grant Cycle Timing .. 48
NAND Flash Controller Interface Timing .............. 50
Synchronous Burst AC Timing ............................ 54
External DMA Request Timing ............................ 55
Enhanced Parallel Peripheral Interface Timing ........ 56
Serial Ports Timing ........................................... 57
Serial Peripheral Interface (SPI) Port—Master Timing 61
Serial Peripheral Interface (SPI) Port—Slave Timing . 62
Universal Asynchronous Receiver-Transmitter
General-Purpose Port Timing ............................. 64
Timer Cycle Timing .......................................... 65
Up/Down Counter/Rotary Encoder Timing ............ 66
SD/SDIO Controller Timing ............................... 67
MXVR Timing ................................................ 69
HOSTDP A/C Timing- Host Read Cycle ................ 70
HOSTDP A/C Timing- Host Write Cycle ............... 71
JTAG Test And Emulation Port Timing ................. 72
(UART) Ports—Receive and Transmit Timing ..... 63