adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 13

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF54x Blackfin processors provide up to four full-
duplex universal asynchronous receiver/transmitter (UART)
ports. Each UART port provides a simplified UART interface to
other peripherals or hosts, supporting full-duplex, DMA-sup-
ported, asynchronous transfers of serial data. A UART port
includes support for five to eight data bits, one or two stop bits,
and none, even, or odd parity. Each UART port supports two
modes of operation:
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
The UART port’s clock rate is calculated as
Where the 16-bit UART Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant eight bits), and EDBO is a bit in the UARTx_GCTL
register.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
UART1 and UART3 feature a pair of UARTxRTS (request to
send) and UARTxCTS (clear to send) signals for hardware flow
purposes. The transmitter hardware is automatically prevented
from sending further data when the UARTxCTS input is de-
asserted. The receiver can automatically de-assert its
UARTxRTS output when the enhanced receive FIFO exceeds a
certain high-water level. The capabilities of the UARTs are fur-
ther extended with support for the Infrared Data Association
(IrDA®) Serial Infrared Physical Layer Link Specification (SIR)
protocol.
• PIO (programmed I/O). The processor sends or receives
• DMA (direct memory access). The DMA controller trans-
• Supporting bit rates ranging from (f
• Supporting data formats from seven to 12 bits per frame.
• Both transmit and receive operations can be configured to
UART Clock Rate
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexi-
ble interrupt timing options are available on the transmit
side.
(f
generate maskable interrupts to the processor.
SCLK
) bits per second.
=
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
----------------------------------------------------------------------------- -
16
(
1 EDBO
–
f SCLK
SCLK
)
×
UART_Divisor
/ 1,048,576) to
Rev. A | Page 13 of 88 | October 2008
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF54x Blackfin processors offer up to two CAN con-
trollers that are communication controllers that implement the
controller area network (CAN) 2.0B (active) protocol. This pro-
tocol is an asynchronous communications protocol used in both
industrial and automotive control systems. The CAN protocol is
well suited for control applications due to its capability to com-
municate reliably over a network since the protocol
incorporates CRC checking, message error tracking, and fault
node confinement.
The ADSP-BF54x Blackfin processors’ CAN controllers offer
the following features:
The electrical characteristics of each network connection are
very demanding, so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF54x Blackfin processors’ CAN module represents only
the controller part of the interface. The controller interface sup-
ports connection to 3.3 V high speed, fault-tolerant, single-wire
transceivers.
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from the processor system clock
(SCLK) through a programmable divider.
TWI CONTROLLER INTERFACE
The ADSP-BF54x Blackfin processors include up to two 2-Wire
Interface (TWI) modules for providing a simple exchange
method of control data between multiple devices. The modules
are compatible with the widely used I
modules offer the capabilities of simultaneous Master and Slave
operation and support for both 7-bit addressing and multime-
dia data arbitration. Each TWI interface uses two pins for
transferring clock (SCLx) and data (SDAx), and supports the
protocol at speeds up to 400K bits/sec. The TWI interface pins
are compatible with 5 V logic levels.
Additionally, the ADSP-BF54x Blackfin processors’ TWI mod-
ules are fully compatible with serial camera control bus (SCCB)
functionality for easier control of various CMOS camera sensor
devices.
• 32 mailboxes (8 receive only, 8 transmit only, 16 config-
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29-
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
• Interrupts, including: TX complete, RX complete, error
urable for receive or transmit).
bit) identifier (ID) message formats.
consumption mode).
and global.
2
C bus standard. The TWI