adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 48

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
External Port Bus Request and Grant Cycle Timing
Table 30
on Page 49
operations for synchronous and for asynchronous BR.
Table 30. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
and
describe external port bus request and grant cycle
Table 31 on Page 49
BR Asserted to CLKOUT Low Setup
CLKOUT Low to BR Deasserted Hold Time
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT Low to BG Asserted Output Delay
CLKOUT Low to BG Deasserted Output Hold
CLKOUT Low to BGH Asserted Output Delay
CLKOUT Low to BGH Deasserted Output Hold
CLKOUT
ADDR19-1
BGH
BR
AMSx
ABE1-0
AWE
ARE
BG
and
Figure 18. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Figure 18
t
BS
and
Rev. A | Page 48 of 88 | October 2008
Figure 19
t
t
t
SD
SD
SD
t
t
DBG
DBH
t
BH
Min
5.0
0.0
t
t
t
t
t
SE
SE
EBH
SE
EBG
Max
5.0
5.0
4.0
4.0
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns