adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet
adsp-bf548
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adsp-bf548 Summary of contents
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FEATURES Up to 533 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs RISC-like register and instruction model Wide range of operating voltages. See on Page 34. Programmable on-chip voltage regulator 400-ball lead-free CSP_BGA package option MEMORY Up to 324K bytes of on-chip memory comprised of instruction SRAM/cache ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 4 System Integration ................................................ 4 Blackfin Processor Peripherals ................................. 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 6 DMA Controllers ................................................ 10 Real-Time Clock ................................................. 11 Watchdog Timer ................................................ 11 Timers ............................................................. 12 Up/Down Counter and Thumbwheel Interface .......... 12 Serial Ports (SPORTs) .......................................... 12 Serial Peripheral Interface (SPI) Ports ...................... 12 UART Ports (UARTs) .......................................... 13 Controller Area Network (CAN) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 GENERAL DESCRIPTION The ADSP-BF54x Blackfin processors are members of the ® Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin pro- cessors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like micro- processor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The ADSP-BF54x Blackfin processors are completely code- and pin-compatible. They differ only with respect to their perfor- mance, on-chip memory, and selection of I/O peripherals. Specific performance, memory, and feature configurations are shown in Table 1. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency ...
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... ASYNC MEMORY BANK 2 (64M BYTES) 2800 0000 ASYNC MEMORY BANK 1 (64M BYTES) 2400 0000 ASYNC MEMORY BANK 0 (64M BYTES) 2000 0000 RESERVED DDR PAGE DDR1 MEM BANK 1 (8M BYTES to 256M BYTES) DDR1 MEM BANK 0 (8M BYTES to 256M BYTES) 0000 0000 Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549 Internal/External Memory Map 1 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 supporting from 64M bit to 512M bit device sizes and 4-, 8-, or 16-bit widths. The controller supports up to 256M bytes per external bank. With 2 external banks, the controller supports up to 512M bytes total. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 • Exceptions. Events that occur synchronously to program flow (that is, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts. Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well explicit software instruction ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 4. System Interrupt Controller (SIC) (Continued) Peripheral IRQ IRQ Source ID DMA20 IRQ (SPORT3 RX) 35 DMA21 IRQ (SPORT3 TX) 36 DMA13 IRQ (EPPI1) 37 DMA14 IRQ (EPPI2, Host DMA) 38 DMA5 IRQ (SPI1) 39 DMA23 IRQ (SPI2) 40 DMA8 IRQ (UART1 RX) 41 DMA9 IRQ (UART1 TX) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 event may be latched in the ILAT register. This register may be read or written while in supervisor mode. Note that general-purpose interrupts can be globally enabled and dis- abled with the STI and CLI instructions, respectively. • CEC interrupt pending register (IPEND). The IPEND reg- ister keeps track of all nested events ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The memory DMA channels of the DMAC1 controller (MDMA2 and MDMA3) can be optionally controlled by the external DMA request input pins. When used in conjunction with the External Bus Interface Unit (EBIU), this handshaked memory DMA (HMDMA) scheme can be used to efficiently exchange data with block-buffered or FIFO-style devices con- nected externally ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The timer is clocked by the system clock (SCLK maximum frequency SCLK TIMERS There are up to two timer units in the ADSP-BF54x Blackfin processors. One unit provides eight general-purpose program- mable timers, and the other unit provides three. Each timer has ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. UART PORTS (UARTS) The ADSP-BF54x Blackfin processors provide up to four full- duplex universal asynchronous receiver/transmitter (UART) ports ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 PORTS Because of their rich set of peripherals, the ADSP-BF54x Blackfin processors group the many peripheral signals to ten ports—referred to as Port A to Port J. Most ports contain 16 pins, though some have less. Many of the associated pins are shared by multiple signals. The ports function as multiplexer controls ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 USB connection without the need for a PC host. The USBDRC module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the On-the-Go (OTG) supplement to the USB 2.0 specification. In host mode, the USB module supports transfers at high speed (480 Mbps), full speed (12 Mbps), and low speed (1 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The MXVR peripheral can wake up the ADSP-BF549 Blackfin processor from sleep mode when a wakeup preamble is received over the network or based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used to wake up the ADSP-BF549 Blackfin processor from the hibernate state ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 − Sleep Operating Mode High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typi- cally an external event or RTC activity will wake up the processor ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 2.7V TO 3.6V SET OF DECOUPLING V DDVR INPUT VOLTAGE (LOW-INDUCTANCE) RANGE 10μH 100nF + 100μF FDS9431A 10μF ZHCS1000 LOW ESR SHORT AND LOW- INDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. Figure 6. Voltage Regulator Circuit CLOCK SIGNALS The ADSP-BF54x Blackfin processors can be clocked by an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DYNAMIC MODIFICATION REQUIRES PLL SEQUENCING PLL CLKIN VCO 0.5x - 64x SCLK CCLK SCLK 133MHz Figure 8. Frequency Modification Methods All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 cessor is ready for data. Conversely, when pulled low, HWAIT is driven high when the processor is ready for data. When the boot sequence completes, the HWAIT pin can be used for other pur- poses. By default, HWAIT functionality is on GPIO port B (PB11). However, if PB11 is otherwise utilized in the system, an ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 NAND flash boot supports the following features: • Device auto detection • Error detection & correction for maximum reliability • No boot stream size limitation • Peripheral DMA via channel 22, providing efficient transfer of all data (excluding the ECC parity data) • Software-configurable boot mode for booting from ...
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... ADSP-BF54x Blackfin processors. EZ-KIT Lite® Evaluation Board For evaluation of ADSP-BF54x Blackfin processors, use the ADSP-BF548 EZ-KIT Lite board available from Analog Devices. Order part number ADZS-BF548-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 the TAP to access the internal features of the processor, allow- ing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The proces- sor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 RELATED DOCUMENTS The following publications that describe the ADSP-BF54x Blackfin processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on www.analog.com: • ADSP-BF54x Blackfin Processor Hardware Reference • ADSP-BF54x Blackfin Processor Peripheral Reference • Blackfin Processor Programming Reference • ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 PIN DESCRIPTIONS ADSP-BF54x Blackfin processors’ pin multiplexing scheme is listed in Table 11 and the pin definitions are listed in Table 11. Pin Multiplexing Primary Pin First Peripheral Function Function (Number Pins) Port A GPIO (16 pins) SPORT2 (8 pins) SPORT3 (8 pins) Port B GPIO (15 pins) TWI1 (2 pins) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 11. Pin Multiplexing Primary Pin First Peripheral Function Function (Number Pins) Port H GPIO (14 pins) UART1 (2 pins) ATAPI_RESET (1 pin) HOST_ADDR (1 pin) HOST_ACK (1 pin) MXVR MRX, MTX, MRXON/GPW 4 (3 pins) Port I GPIO (16 pins) Async Addr10–25 (16 pins) Port J GPIO (14 pins) Async CTL and MISC 1 Port connections may be inputs or outputs after power up depending on the model and boot mode chosen ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions Pin Name Port A: GPIO/SPORT2–3/TMR4–7 PA0/TFS2 PA1/DT2SEC/TMR4 PA2/DT2PRI PA3/TSCLK2 PA4/RFS2 PA5/DR2SEC/TMR5 PA6/DR2PRI PA7/RSCLK2/TACLK0 PA8/TFS3/TACLK1 PA9/DT3SEC/TMR6 PA10/DT3PRI/TACLK2 PA11/TSCLK3/TACLK3 PA12/RFS3/TACLK4 PA13/DR3SEC/TMR7/TACLK5 PA14/DR3PRI/TACLK6 PA15/RSCLK3/TACLK7 and TACI7 Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3 PB0/SCL1 PB1/SDA1 PB2/UART3RTS PB3/UART3CTS PB4/UART2TX PB5/UART2RX/TACI2 PB6/UART3TX ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port C: GPIO/SPORT0/SD Controller/MXVR (MOST) PC0/TFS0 PC1/DT0SEC/MMCLK PC2/DT0PRI PC3/TSCLK0 PC4/RFS0 PC5/DR0SEC/MBCLK PC6/DR0PRI PC7/RSCLK0 PC8/SD_D0 PC9/SD_D1 PC10/SD_D2 PC11/SD_D3 PC12/SD_CLK PC13/SD_CMD Port D: GPIO/PPI0–2/SPORT 1/Keypad/Host DMA PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18 PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20 PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 PD4/PPI1_D4/HOST_D12/RFS1/PPI0_D22 PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port E: GPIO/SPI0/UART0-1/PPI1/TWI0/Keypad 3 PE0/SPI0SCK/KEY_COL7 3 PE1/SPI0MISO/KEY_ROW6 PE2/SPI0MOSI/KEY_COL6 PE3/SPI0SS/KEY_ROW5 3 PE4/SPI0SEL1/KEY_COL PE5/SPI0SEL2/KEY_ROW4 PE6/SPI0SEL3/KEY_COL4 PE7/UART0TX/KEY_ROW7 PE8/UART0RX/TACI0 PE9/UART1RTS PE10/UART1CTS PE11/PPI1_CLK PE12/PPI1_FS1 PE13/PPI1_FS2 PE14/SCL0 PE15/SDA0 Port F: GPIO/PPI0/Alternate ATAPI Data PF0/PPI0_D0/ATAPI_D0A PF1/PPI0_D1/ATAPI_D1A PF2/PPI0_D2/ATAPI_D2A PF3/PPI0_D3/ATAPI_D3A PF4/PPI0_D4/ATAPI_D4A PF5/PPI0_D5/ATAPI_D5A PF6/PPI0_D6/ATAPI_D6A PF7/PPI0_D7/ATAPI_D7A PF8/PPI0_D8/ATAPI_D8A PF9/PPI0_D9/ATAPI_D9A PF10/PPI0_D10/ATAPI_D10A ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port G: GPIO/PPI0/SPI1/PPI2/Up-Down Counter/CAN0–1/Host DMA/MXVR (MOST)/Alternate ATAPI Addr PG0/PPI0_CLK/TMRCLK PG1/PPI0_FS1 PG2/PPI0_FS2/ATAPI_A0A PG3/PPI0_D16/ATAPI_A1A PG4/PPI0_D17/ATAPI_A2A PG5/SPI1SEL1/HOST_CE/PPI2_FS2/CZM PG6/SPI1SEL2/HOST_RD/PPI2_FS1 PG7/SPI1SEL3/HOST_WR/PPI2_CLK PG8/SPI1SCK PG9/SPI1MISO PG10/SPI1MOSI PG11/SPI1SS/MTXON PG12/CAN0TX PG13/CAN0RX/TACI4 PG14/CAN1TX PG15/CAN1RX/TACI5 Port H: GPIO/AMC/EXTDMA/UART1/PPI0–2/ATAPI Interface/Up-Down Counter/TMR8-10/Host ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port I: GPIO/AMC 6 PI0/A10 6 PI1/A11 6 PI2/A12 6 PI3/A13 6 PI4/A14 6 PI5/A15 6 PI6/A16 6 PI7/A17 6 PI8/A18 6 PI9/A19 6 PI10/A20 6 PI11/A21 6 PI12/A22 6 PI13/A23 6 PI14/A24 6 PI15/A25/NR_CLK Port J: GPIO/AMC/ATAPI Controller PJ0/ARDY/WAIT 7 PJ1/ND_CE PJ2/ND_RB PJ3/ATAPI_DIOR PJ4/ATAPI_DIOW PJ5/ATAPI_CS0 PJ6/ATAPI_CS1 PJ7/ATAPI_DMACK PJ8/ATAPI_DMARQ PJ9/ATAPI_INTRQ PJ10/ATAPI_IORDY 8 PJ11/BR 6 PJ12/BG ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name DDR1 Memory Interface DA0–12 DBA0–1 DQ0–15 DQS0–1 DQM0–1 DCLK0–1 DCLK0–1 DCS0–1 DCLKE DRAS DCAS DWE DDR_VREF DDR_VSSR Asynchronous Memory Interface A1-3 D0-15/ND_D0-15/ATAPI_D0-15 AMS0–3 ABE0 /ND_CLE ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Mode Control Pins BMODE0–3 JTAG Port Pins TDI TDO TRST TMS TCK EMU Voltage Regulator OUT OUT Real Time Clock RTXO RTXI Clock (PLL) Pins CLKIN CLKOUT XTAL CLKBUF EXT_WAKE RESET ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Internal Supply Voltage DDINT Internal Supply Voltage 3 V External Supply Voltage DDEXT External Supply Voltage External Supply Voltage V USB External Supply Voltage DDUSB V MXVR PLL Supply Voltage DDMP ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 13 and Table 15 describe the voltage/frequency require- ments for the ADSP-BF54x Blackfin processors’ clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. describes the phase-locked loop operating conditions. Table 13. Core Clock Requirements—533 MHz Speed Grade ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ELECTRICAL CHARACTERISTICS Parameter V High Level Output Voltage for 3.3V I/O OH High Level Output Voltage for 2.5V I/O V High Level Output Voltage OHDDR V Low Level Output Voltage for 3.3V I/O OL Low Level Output Voltage for 2.5V I/O V Low Level Output Voltage OLDDR I High Level Input Current IH I High Level Input Current ...
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... DD-IDLE 1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP- BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 processors. specification for the listed test conditions, including the dynamic component as a function of voltage (V quency (Table There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 18. Dynamic Current in CCLK Domain (mA, with ASF = 1.0) f 0.90 V 0.95 V CCLK 2 (MHz) 100 29.7 31.6 200 55.3 58.9 300 80.8 85.8 400 N/A 112.2 500 N/A N/A 533 N/A N/A 1 The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of 2 Valid frequency and voltage ranges are model-specific. See ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 19 nent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli- ability ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TIMING SPECIFICATIONS Timing specifications are detailed in this section. Clock and Reset Timing Table 22 and Figure 10 describe Clock Input and Reset Timing. Table 23 and Figure 11 describe Clock Out Timing. Table 22. Clock Input and Reset Timing Parameter Timing Requirements CLKIN Period ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 23. Clock Out Timing Parameter Switching Characteristics 1,2 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL 1 The t value is the inverse of the f specification. Reduced supply voltages affect the best-case value of 7.5 ns listed here. SCLK SCLK 2 The t value does not account for the effects of jitter. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Read Cycle Timing Table 24 and Table 25 on Page 43 and Figure 12 on Page 43 describe asynchronous memory read cycle opera- tions for synchronous and for asynchronous ARDY. Table 24. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 25. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Write Cycle Timing Table 26 and Table 27 on Page 45 and Figure 14 on Page 45 describe asynchronous memory write cycle opera- tions for synchronous and for asynchronous ARDY. Table 26. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Parameter Timing Requirements t ARDY Setup Before the Falling Edge of CLKOUT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 27. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANW t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR1 SDRAM Read Cycle Timing Table 28 and Figure 16 describe DDR1 SDRAM Read Cycle Timing. Table 29 and Figure 17 describe DDR1 SDRAM Write Cycle Timing. Table 28. DDR1 SDRAM Read Cycle Timing, V Parameter Timing Requirements t Access Window Access Window of DQS to CK ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR1 SDRAM Write Cycle Timing Table 29. DDR1 SDRAM Write Cycle Timing, V Parameter Switching Characteristics t Clock Period CK t Clock High Pulse Width CH t Clock Low Pulse Width CL t Write CMD to First DQS DQSS t DQ/DQM Setup to DQS DS t DQ/DQM Hold to DQS DH t DQS Falling to CK Rising (DQS Setup) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External Port Bus Request and Grant Cycle Timing Table 30 and Table 31 on Page 49 and Figure 18 on Page 49 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 30. External Port Bus Request and Grant Cycle Timing with Synchronous BR ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 31. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Timing Requirements t BR Pulsewidth WBR Switching Characteristics t CLKOUT Low to AMSx, Address, and AREAWE Disable SD t CLKOUT Low to AMSx, Address, and ARE/AWE Enable SE t CLKOUT Low to BG Asserted Output Delay ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 NAND Flash Controller Interface Timing Table 32 and Figure 20 on Page 51 through Page 53 describe NAND Flash Controller Interface operations. Table 32. NAND Flash Controller Interface Timing Parameter Write Cycle Switching Characteristics t ND_CE Setup Time to AWE Low CWL t ND_CE Hold Time From AWE High ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 t CWL ND_CE ND_CLE t CLHWL t ALLWL ND_ALE t WP AWE t DWS ND_D Figure 20. NAND Flash Controller Interface Timing t CWL ND_CE t CLLWL ND_CLE ND_ALE t ALHWL t WP AWE t DWS ND_D Figure 21. NAND Flash Controller Interface Timing Rev Page October 2008 t CH ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ND_CE ND_CLE ND_ALE AWE ARE ND_D Figure 22. NAND Flash Controller Interface Timing ND_CE ND_CLE ND_ALE AWE ARE ND_D Figure 23. NAND Flash Controller Interface Timing t CWL t CLLWL t ALHWL WHWL DWS t DWH − Data Write Operation t CRL t RC ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 t CWL ND_CE ND_CLE t CLHWL ND_ALE t WP AWE ARE t DWS ND_D Figure 24. NAND Flash Controller Interface Timing Rev Page October 2008 t CLH WHWL t DWH t DRS t DWH − Write Followed by Read Operation ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Synchronous Burst AC Timing Table 33 and Figure 25 on Page 54 describe Synchronous Burst AC operations. Table 33. Synchronous Burst AC Timing Parameter Timing Requirements t DATA15-0 Setup Before NR_CLK NDS t DATA15-0 Hold After NR_CLK NDH t WAIT Setup Before NR_CLK NWS t WAIT Hold After NR_CLK NWH Switching Characteristics ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External DMA Request Timing Table 34 and Figure 26 describe the External DMA Request operations. Table 34. External DMA Request Timing Parameter Timing Parameters t DMARx Asserted to CLKOUT High Setup DR t CLKOUT High to DMARx Deasserted Hold Time DH t DMARx Active Pulse Width DMARACT t DMARx Inactive Pulse Width ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Enhanced Parallel Peripheral Interface Timing Table 35 and Figure 27 on Page 56 describes enhanced parallel peripheral interface operations. Table 35. Enhanced Parallel Peripheral Interface Timing Parameter Timing Requirements t PPIx_CLK Width PCLKW t PPIx_CLK Period PCLK Timing Requirements - GP Input and Frame Capture Modes t External Frame Sync Setup Before PPIx_CLK ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Ports Timing Table 36 through Table 39 on Page 58 and through Figure 29 on Page 60 describe serial port operations. Table 36. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) ...
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... ADSP-BF54x Table 38. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable Delay from External TSCLKx DTENE t Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DATA RECEIVE—INTERNAL CLOCK DRIVE SAMPLE EDGE EDGE t SCLKIW RSCLKx t DFSI t t HOFSI SFSI RFSx t SDRI DRx NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE SAMPLE EDGE EDGE ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 EXTERNAL RFS IN MULTICHANNEL MODE WITH MFD = 0 RSCLKx RFSx DTx LATE EXTERNAL TFS TSCLKx TFSx DTx DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTTE/I t DTENLFS t DTENE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTTE/I t DTENLFS t DTENE/I 1ST BIT t DDTLFSE Figure 29. External Late Frame Sync Rev ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Master Timing Table 40 and Figure 30 describe SPI port master operations. Table 40. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SPIxSCK Edge (Data Input Setup) SSPIDM t SPIxSCK Sampling Edge to Data Input Invalid ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Slave Timing Table 41 and Figure 31 describe SPI port slave operations. Table 41. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period SPICLK ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Figure 32 describes the UART ports receive and transmit opera- tions. The maximum baud rate is SCLK/16. There is some latency between the generation of internal UART interrupts CLKOUT (SAMPLE CLOCK) UARTx Rx RECEIVE INTERNAL UART RECEIVE ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 General-Purpose Port Timing Table 42 and Figure 33 describe general-purpose port operations. Table 42. General-Purpose Port Timing Parameter Timing Requirement t General-Purpose Port Pin Input Pulse Width WFI Switching Characteristic t General-Purpose Port Pin Output Delay from CLKOUT Low GPOD CLKOUT GPP OUTPUT GPP INPUT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Timer Cycle Timing Table 43 and Figure 34 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 43. Timer Cycle Timing Parameter Timing Characteristics ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Up/Down Counter/Rotary Encoder Timing Table 44 and Figure 35 describe up/down counter/rotary encoder timing. Table 44. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirements t Up/Down Counter/Rotary Encoder Input Pulse Width WCOUNT t Counter Input Setup Time Before CLKOUT Low CIS t Counter Input Hold Time After CLKOUT Low ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SD/SDIO Controller Timing Table 45 and Figure 36 describe SD/SDIO Controller Timing. Table 46 and Figure 37 describe SD/SDIO controller (high speed) timing. Table 45. SD/SDIO Controller Timing Parameter Timing Requirements t Input Setup Time ISU t Input Hold Time IH Switching Characteristics f Clock Frequency Data Transfer Mode ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 46. SD/SDIO Controller Timing (High Speed Mode) Parameter Timing Requirements t Input Setup Time ISU t Input Hold Time IH Switching Characteristics f Clock Frequency Data Transfer Mode PP t Clock Low Time WL Clock High Time Clock Rise Time TLH t Clock Fall Time THL ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 MXVR Timing Table 47 and Table 48 describe the MXVR timing requirements. Figure 5 illustrates the MOST connection. Table 47. MXVR Timing—MXI Center Frequency Requirements Parameter f MXI Center Frequency (256 Fs) _256 MXI f MXI Center Frequency (384 Fs) _384 MXI f MXI Center Frequency (512 Fs) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 − HOSTDP A/C Timing Host Read Cycle Table 49 and Figure 38 describe the HOSTDP A/C host read cycle timing requirements. Table 49. Host Read Cycle Timing Requirements Parameter Timing Requirements t HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge SADRDL t HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 − HOSTDP A/C Timing Host Write Cycle Table 50 and Figure 39 describe the HOSTDP A/C host write cycle timing requirements. Table 50. Host Write Cycle Timing Requirements Parameter Timing Requirements t HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge SADWRL t HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge HADWRH ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 JTAG Test And Emulation Port Timing Table 51 and Figure 40 describe JTAG port operations. Table 51. JTAG Port Timing Parameter Timing Parameters t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTPUT DRIVE CURRENTS Figure 41 through Figure 49 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF54x Blackfin processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 80 o 2.25V, +105 2.5V, + ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 50 o 2.5V, + 2.7V, - -10 -20 -30 VOL -40 o 2.5V, +25 C 2.7V, -40 -50 0 0.5 1 1.5 SOURCE VOLTAGE (V) Figure 47. Drive Current -10 -20 o 2.25V, +105 C -30 -40 o 2.5V, +25 C VOL -50 2.75V, -40 -60 0 0.5 1 1.5 SOURCE VOLTAGE (V) Figure 48. Drive Current E (Low -10 -20 -30 -40 o 2.7V, +105 C -50 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 REFERENCE SIGNAL t DIS_MEASURED t t DIS ENA V OH (MEASURED) V (MEASURED (MEASURED (MEASURED) t DECAY OUTPUT STOPS DRIVING HIGH IMPEDANCE STATE Figure 51. Output Enable/Disable Example System Hold Time Calculation To determine the data output hold time in a particular system, using the equation given above. Choose ΔV ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 12 10 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 54. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 3.65 V DDEXT 12 10 RISE TIME 100 LOAD CAPACITANCE (pF) Figure 55. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 100 150 LOAD CAPACITANCE (pF) Figure 60. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 2.7V DDDDR 132 128 124 120 116 112 108 0 50 100 LOAD CAPACITANCE (pF) Figure 61. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board use ( Ψ CASE JT where: T =junction temperature ( case temperature ( C) measured by customer at top cen- CASE ter of package. Ψ = from Table power dissipation (see Table 16 on Page 37 D calculate P D Values of θ ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 400-BALL CSP_BGA PACKAGE Table 53 lists the CSP_BGA package by signal for the ADSP-BF549. Table 54 on Page 82 lists the CSP_BGA package by ball number. Table 53. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal A1 B2 DA4 A2 A2 DA5 A3 B3 DA6 ABE0 C17 DA7 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 53. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal MLF_P E4 PC5 MXI C2 PC6 MXO C1 PC7 NMI C11 PC8 PA0 U12 PC9 PA1 V12 PC10 PA2 W12 PC11 PA3 Y12 PC12 PA4 W11 PC13 PA5 V11 PD0 PA6 Y11 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 53. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal TCK V3 V DDDDR TDI V5 V DDDDR TDO V4 V DDDDR TMS U5 V DDDDR TRST T5 V DDEXT USB_DM E2 V DDEXT USB_DP E1 V DDEXT USB_ID G3 V DDEXT USB_RSET D3 V DDEXT USB_VBUS D2 V DDEXT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 54 lists the CSP_BGA package by ball number for the ADSP-BF549. Table 53 on Page 79 lists the CSP_BGA package by signal. Table 54. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A1 GND PI0 C3 A4 PI2 C4 A5 PI4 C5 A6 PI6 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 54. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. J1 PF1 L1 J2 PC2 L2 J3 PC1 L3 J4 PG0 L4 J5 PC6 DDINT J7 GND L7 J8 GND L8 J9 GND L9 J10 GND L10 J11 GND L11 J12 GND L12 J13 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 54. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. U1 PD8 V1 U2 PD9 V2 U3 PD15 V3 U4 PD14 V4 U5 TMS V5 U6 PB3 V6 U7 PB10 V7 U8 GND DDINT U10 PA8 V10 U11 PA7 V11 U12 PA0 V12 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 63 lists the top view of the BGA ball configuration KEY SUPPLIES DDINT DDDDR DDMP V REFERENCES: DDR_V , USB_V R DDEXT REF GROUNDS: GND , DDR_V G GND MP VR OUT V NC I/O SIGNALS Figure 63 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTLINE DIMENSIONS Dimensions for the 17 mm × CSP_BGA package in Figure 64 are shown in millimeters. 17.00 BSC SQ A1 BALL INDICATOR TOP VIEW SIDE VIEW 1.70 MAX DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM, WITH THE EXCEPTION OF BALL DIAMETER. ...
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... ADSP-BF544BBCZ-5A –40°C to 85°C ADSP-BF547BBCZ-5A –40°C to 85°C ADSP-BF548BBCZ-5A –40°C to 85° RoHS compliant part 2 The ADSP-BF549 is available for automotive use only. Please contact your local ADI product representative or authorized distributor for specific automotive product ordering information ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 © 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06512-0-10/08(A) Rev Page October 2008 ...