adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 70

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOSTDP A/C Timing
Table 49
cycle timing requirements.
Table 49. Host Read Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
NM (Not Measured) — This parameter is not measured because the time for which HOST_ACK is low is system design dependent.
SADRDL
HADRDH
RDWL
RDWL
RDWH
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
DDARWH
ACC
HDARWH
HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge
HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge
HOST_RD Pulse Width Low (ACK Mode)
HOST_RD Pulse Width Low (INT Mode)
HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and
HOST_WR Falling Edge
HOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode)
Data Valid Prior HOST_ACK Rising Edge (ACK Mode)
Host_ACK Assertion Delay After HOST_RD/HOST_CE (ACK Mode)
HOST_ACK Low Pulse-Width for Read Access (ACK Mode)
Data Disable After HOST_RD
Data Valid After HOST_RD Falling Edge (INT Mode)
Data Hold After HOST_RD Rising Edge
and
Figure 38
−
describe the HOSTDP A/C host read
Host Read Cycle
HOST_ADDR
HOST_D15-0
HOST_CE
HOST_ACK
HOST_RD
t
Figure 38. HOSTDP A/C
Rev. A | Page 70 of 88 | October 2008
SADRDL
t
DRDYRDL
t
SDATRDY
t
ACC
t
RDYPRD
t
RDWL
−
Host Read Cycle
t
DRDHRDY
t
HDARWH
1.5 × t
t
4
2.5
t
2 × t
0
1.0
DRDYRDL
SCLK
t
– 4.0
HADRDH
SCLK
t
RDWH
+ t
SCLK
RDYPRD
+ 8.7
t
Min
DDARWH
+ t
DRDHRDY
1.5 × t
NM
8.0
1.5 × t
1
SCLK
SCLK
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns