adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 43

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Table 25. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
S = number of programmed setup cycles, RA = number of programmed read access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SDAT
HDAT
DANR
HAA
DO
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
ARE
ARDY
AOE
DATA15–0
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
Output Delay After CLKOUT
Output Hold After CLKOUT
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
2 CYCLES
SETUP
t
DO
Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
t
DANR
PROGRAMMED READ ACCESS
t
2
DO
2
Rev. A | Page 43 of 88 | October 2008
4 CYCLES
1
BE, ADDRESS
ACCESS EXTENDED
t
t
HO
SDAT
READ
Min
5.0
0.8
0.0
0.3
1 CYCLE
HOLD
t
HDAT
t
HAA
Max
(S + RA – 2) × t
6.0
t
HO
SCLK
Unit
ns
ns
ns
ns
ns
ns