adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 20

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
cessor is ready for data. Conversely, when pulled low, HWAIT is
driven high when the processor is ready for data. When the boot
sequence completes, the HWAIT pin can be used for other pur-
poses. By default, HWAIT functionality is on GPIO port B
(PB11). However, if PB11 is otherwise utilized in the system, an
alternate boot Host wait (HWAITA) signal can be enabled on
GPIO port H (PH7) by programming the
OTP_ALTERNATE_HWAIT bit in the PBS00L OTP
memory page.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
• Idle
• Boot from 8- or 16-bit external flash memory
• Boot from 16-bit asynchronous FIFO (BMODE=0x2)—In
• Boot from serial SPI memory, EEPROM or flash
• Boot from SPI host device (BMODE=0x4)—The processor
• Boot from serial TWI memory, EEPROM or flash
processor goes into idle. The idle boot mode helps to
recover from illegal operating modes, in case the OTP
memory is misconfigured.
(BMODE=0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and, depend-
ing on instructions contained in the header, the boot kernel
performs an 8- or 16-bit boot or starts program execution
at the address provided by the header. By default, all con-
figuration settings are set for the slowest device possible (3-
cycle hold time; 15-cycle R/W access times; 4-cycle setup).
The ARDY is not enabled by default. It can, however, be
enabled by OTP programming. Similarly, all interface
behavior and timings can be customized through OTP pro-
gramming. This includes activation of burst-mode or page-
mode operation. In this mode, all asynchronous interface
signals are enabled at the port muxing level.
this mode, the boot kernel starts booting from address
0x2030 0000. Every 16-bit word that the boot kernel has to
read from the FIFO must be requested by a low pulse on
the DMAR1 pin.
(BMODE=0x3)—8-, 16-, 24- or 32-bit addressable devices
are supported. The processor uses the PE4 GPIO pin to
select a single SPI EEPROM or flash device and uses SPI0
to submit a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SPI0SEL1
and SPI0MISO pins. By default, a value of 0x85 is written to
the SPI0_BAUD register.
operates in SPI slave mode (using SPI0) and is configured
to receive the bytes of the .LDR file from an SPI host (mas-
ter) agent. The HWAIT signal must be interrogated by the
host before every transmitted byte. A pull-up resistor is
required on the SPI0SS input. A pull-down on the serial
clock (SPI0SCK) may improve signal quality and booting
robustness.
(BMODE=0x5)—The processor operates in master mode
(using TWI0) and selects the TWI slave with the unique ID
0xA0. The processor submits successive read commands to
−
no boot mode (BMODE=0x0)—In this mode, the
Rev. A | Page 20 of 88 | October 2008
• Boot from TWI host (BMODE=0x6)—The TWI host agent
• Boot from UART host (BMODE=0x7)—In this mode, the
• Boot from (DDR1) SDRAM (BMODE=0xA)—In this
• Boot from 8-bit and 16-bit external NAND flash memory
the memory device starting at 2-byte internal address
0x0000 and begins clocking data into the processor. The
TWI memory device should comply with Philips I
Specification version 2.1 and have the capability to auto-
increment its internal address counter such that the con-
tents of the memory device can be read sequentially. By
default, a prescale value of 0xA and CLKDIV value of
0x0811 is used. Unless altered by OTP settings, an I
memory that takes two address bytes is assumed. Develop-
ment tools ensure that data that is booted to memories that
cannot be accessed by the Blackfin core is written to an
intermediate storage place and then copied to the final des-
tination via Memory DMA.
selects the slave with the unique ID 0x5F. The processor
(using TWI0) replies with an acknowledgement, and the
host can then download the boot stream. The TWI host
agent should comply with Philips I
sion 2.1. An I
processor at a time when booting multiple processors from
a single TWI.
processor uses UART1 as the booting source. Using an
autobaud handshake sequence, a boot-stream-formatted
program is downloaded by the host. The host agent selects
a bit rate within the UART’s clocking capabilities.
When performing the autobaud, the UART expects a “@”
(0x40) character (eight data bits, one start bit, one stop bit,
no parity bit) on the UART1RX pin to determine the bit
rate. It then replies with an acknowledgement, which is
composed of 4 bytes (0xBF, the value of UART1_DLL, the
value of UART1_DLH, and finally 0x00). The host can then
download the boot stream. The processor deasserts the
UART1RTS output to hold off the host; UART1CTS func-
tionality is not enabled at boot time.
mode, the boot kernel starts booting from address
0x0000 0010. This is a warm boot scenario only. The
SDRAM is expected to contain a valid boot stream and the
SDRAM controller must have been configured by the OTP
settings.
(BMODE=0xD)—In this mode, auto detection of the
NAND flash device is performed. The processor configures
PORTJ GPIO pins PJ1 and PJ2 to enable the ND_CE and
ND_RB signals, respectively. For correct device operation,
pull-up resistors are required on both ND_CE (PJ1) and
ND_RB (PJ2) signals. By default, a value of 0x0033 is writ-
ten to the NFC_CTL register. The booting procedure
always starts by booting from byte 0 of block 0 of the
NAND flash device. In this boot mode, the HWAIT signal
does not toggle. The respective GPIO pin remains in the
high-impedance state.
2
C multiplexer can be used to select one
2
C Bus Specification ver-
2
C Bus
2
C