adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 10

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
ADSP-BF54x Blackfin processors have multiple, independent
DMA channels that support automated data transfers with min-
imal overhead for the processor core. DMA transfers can occur
between the ADSP-BF54x processors’ internal memories and
any of its DMA-capable peripherals. Additionally, DMA trans-
fers can be accomplished between any of the DMA-capable
• CEC interrupt pending register (IPEND). The IPEND reg-
• SIC interrupt mask register (SIC_IMASKx). This register
• SIC interrupt status register (SIC_ISRx). As multiple
• SIC interrupt wakeup enable register (SIC_IWRx). By
event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. Note that
general-purpose interrupts can be globally enabled and dis-
abled with the STI and CLI instructions, respectively.
ister keeps track of all nested events. A set bit in the IPEND
register indicates the event is currently active or nested at
some level. This register is updated automatically by the
controller but may be read while in supervisor mode.
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and is processed by the sys-
tem when asserted. A cleared bit in the register masks the
peripheral event, preventing the processor from servicing
the event.
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled or in Sleep mode when the event is generated.
(For more information, see Dynamic Power Management
on Page
16.)
Table 4 on Page
8.
Rev. A | Page 10 of 88 | October 2008
peripherals and external devices connected to the external
memory interfaces, including DDR1 and asynchronous mem-
ory controllers.
While the USB controller and MXVR have their own dedicated
DMA controllers, the other on-chip peripherals are managed by
two centralized DMA controllers, called DMAC1 (32-bit) and
DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA
controller manages 12 independent peripheral DMA channels,
as well as two independent memory DMA streams. The
DMAC1 controller masters high bandwidth peripherals over a
dedicated 32-bit DMA access bus (DAB32). Similarly, the
DMAC0 controller masters most serial interfaces over the 16-bit
DAB16 bus. Individual DMA channels have fixed access prior-
ity on the DAB buses. DMA priority of peripherals is managed
by a flexible peripheral-to-DMA channel assignment scheme.
All four DMA controllers use the same 32-bit DCB bus to
exchange data with L1 memory. This includes L1 ROM, but
excludes scratchpad memory. Fine granulation of L1 memory
and special DMA buffers minimize potential memory conflicts
when the L1 memory is accessed simultaneously by the core.
Similarly, there are dedicated DMA buses between the external
bus interface unit (EBIU) and the three DMA controllers
(DMAC1, DMAC0, and USB) that arbitrate DMA accesses to
external memories and the boot ROM.
The ADSP-BF54x Blackfin processors’ DMA controllers sup-
port both 1-dimensional (1D) and 2-dimensional (2D) DMA
transfers. DMA transfer initialization can be implemented from
registers or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the ADSP-BF54x Black-
fin processors’ DMA controllers include:
In addition to the dedicated peripheral DMA channels, the
DMAC1 and DMAC0 controllers each feature two memory
DMA channel pairs for transfers between the various memories
of the ADSP-BF54x Blackfin processors systems. This enables
transfers of blocks of data between any of the memories—
including external DDR1, ROM, SRAM, and flash memory—
with minimal processor intervention. Like peripheral DMAs,
memory DMA transfers can be controlled by a very flexible
descriptor-based methodology or by a standard register-based
autobuffer mechanism.
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
• 1D or 2D DMA using a linked list of descriptors
• 2D DMA using an array of descriptors, specifying only the
full or fractionally full buffer
base DMA address within a common page