adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 12

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
The timer is clocked by the system clock (SCLK) at a maximum
frequency of f
TIMERS
There are up to two timer units in the ADSP-BF54x Blackfin
processors. One unit provides eight general-purpose program-
mable timers, and the other unit provides three. Each timer has
an external pin that can be configured either as a pulse width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input on the TMRx pins, an external clock
TMRCLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the four
UARTs and the CAN controllers to measure the width of the
pulses in the data stream to provide a software auto-baud detect
function for the respective serial channels.
The timers can generate interrupts to the processor core, pro-
viding periodic events for synchronization to either the system
clock or to a count of external signals.
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of periodic operating
system interrupts.
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
A 32-bit up/down counter is provided that can sense the 2-bit
quadrature or binary codes typically emitted by industrial drives
or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input pin or by two edge
detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary regis-
ters enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
SERIAL PORTS (SPORTS)
The ADSP-BF54x Blackfin processors incorporate up to four
dual-channel synchronous serial ports (SPORT0, SPORT1,
SPORT2, SPORT3) for serial and multiprocessor communica-
tions. The SPORTs support the following features:
• I
• Bidirectional operation. Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports. Each port has
pendent transmit and receive pins, enabling up to eight
channels of I
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
2
S capable operation.
SCLK
.
2
S stereo audio.
Rev. A | Page 12 of 88 | October 2008
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF54x Blackfin processors have up to three SPI-
compatible ports that allow the processor to communicate with
multiple SPI-compatible devices.
Each SPI port uses three pins for transferring data: two data pins
(master output-slave input, SPIxMOSI, and master input-slave
output, SPIxMISO) and a clock pin (serial clock, SPIxSCK). An
SPI chip select input pin (SPIxSS) lets other SPI devices select
the processor, and three SPI chip select output pins per SPI port
SPIxSELy let the processor select other SPI devices. The SPI
select pins are reconfigured general-purpose I/O pins. Using
these pins, the SPI ports provide a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as
Where the 16-bit SPI_BAUD register contains a value of
2 to 65,535.
• Clocking. Each transmit and receive port can either use an
• Word length. Each SPORT supports serial data words from
• Framing. Each transmit and receive port can run with or
• Companding in hardware. Each SPORT can perform
• DMA operations with single-cycle overhead. Each SPORT
• Interrupts. Each transmit and receive port generates an
• Multichannel capability. Each SPORT supports 128 chan-
external serial clock or generate its own, in frequencies
ranging from (f
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SPI Clock Rate
SCLK
/131,070) Hz to (f
=
--------------------------------
2 SPI_Baud
×
f
SCLK
SCLK
/2) Hz.