adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 65

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Timer Cycle Timing
Table 43
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 43. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
t
t
Switching Characteristic
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs.
WL
WH
TIS
TIH
HTO
TOD
and
SCLK
Figure 34
TIMER OUTPUT
/2) MHz.
TIMER INPUT
Timer Pulse Width Input Low (Measured in SCLK Cycles)
Timer Pulse Width Input High (Measured in SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output (Measured in SCLK Cycles)
Timer Output Update Delay After CLKOUT High
CLK OUT
describe timer expired operations. The
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. A | Page 65 of 88 | October 2008
t
TIS
Figure 34. Timer Cycle Timing
2
2
t
WH,
t
t
WL
TIH
1
1
t
HTO
t
TOD
Min
t
t
6.5
–1
1t
SCLK
SCLK
SCLK
+1
+1
Max
(2
6
32
– 1)t
SCLK
Unit
ns
ns
ns
ns
ns
ns