adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 35

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Table 13
ments for the ADSP-BF54x Blackfin processors’ clocks. Take
care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock.
describes the phase-locked loop operating conditions.
Table 13. Core Clock Requirements—533 MHz Speed Grade
1
Table 14. Phase-Locked Loop Operating Conditions
Table 15. System Clock Requirements
1
2
Parameter
f
f
f
f
f
See the
Parameter
f
Parameter
f
f
f
Rounded number. Actual test specification is SCLK period of 7.5 ns. See
CCLK
CCLK
CCLK
CCLK
CCLK
VCO
SCLK
SCLK
SCLK
must be less than or equal to f
Ordering Guide on Page
and
Table 15
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Voltage Controlled Oscillator (VCO) Frequency
Condition
V
V
DDEXT
DDEXT
describe the voltage/frequency require-
= 3.3 V or 2.5 V, V
= 3.3 V or 2.5 V, V
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
87.
CCLK
.
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
=1.20 V minimum)
=1.14 V minimum)
=1.045 V minimum)
=0.95 V minimum)
=0.90 Vminimum)
≥ 1.14 V
< 1.14 V
Rev. A | Page 35 of 88 | October 2008
Table 14
1
1
Table 23 on Page
1
41.
Internal Regulator Setting
1.25 V
1.20 V
1.10 V
1.00 V
0.95 V
Min
50
Max
Maximum f
Max
133
100
2
Max
533
500
444
400
333
CCLK
Unit
MHz
MHz
MHz
MHz
MHz
Unit
MHz
Unit
MHz
MHz