adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 72

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
JTAG Test And Emulation Port Timing
Table 51
Table 51. JTAG Port Timing
1
2
3
DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, CLKOUT, A3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, RESET, NMI,
50 MHz Maximum
System Outputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
BMODE3–0.
and
Figure 40
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse-Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
OUTPUTS
SYSTEM
TCK
TMS
TDO
INPUTS
SYSTEM
TDI
2
(measured in TCK cycles)
t
DSYS
t
DTDO
t
Rev. A | Page 72 of 88 | October 2008
SSYS
t
STAP
1
3
1
Figure 40. JTAG Port Timing
t
TCK
t
HSYS
t
HTAP
–
1, MFS.
Min
20
4
4
4
11
4
0
Max
10
16.5
Unit
ns
t
ns
ns
ns
ns
ns
ns
TCK