adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 33

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Table 12. Pin Descriptions (Continued)
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
Mode Control Pins
BMODE0–3
JTAG Port Pins
TDI
TDO
TRST
TMS
TCK
EMU
Voltage Regulator
VR
Real Time Clock
RTXO
RTXI
Clock (PLL) Pins
CLKIN
CLKOUT
XTAL
CLKBUF
EXT_WAKE
RESET
NMI
Supplies
V
V
V
V
V
V
GND
V
GND
I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.
Refer to
To use the SPI memory boot, SPI0SCK should have a pulldown, SPI0MISO should have a pullup, and SPI0SEL1 is used as the CS with a pullup.
HWAIT/HWAITA should be pulled high or low to configure polarity. See
GPW functionality is available when MXVR is not present or unused.
This pin should not be used as GPIO if booting in mode 1.
This pin should always be enabled as ND_CE in software and pulled high with a resistor when using NAND flash.
This pin should always be enabled as BR in software and pulled high to enable Async access.
If the USB is used in device mode only, the USB_ID pin should be either pulled high or left unconnected.
This pin is an output only during initialization of USB OTG session request pulses. Therefore, host mode or OTG type A mode requires that an external voltage source of
To ensure proper operation, the power pins should be driven to their specified level even if the associated peripheral is not used in the application.
This pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to V
5V, at 8mA or more per the OTG specification, be applied to this pin. Other OTG modes require that this external voltage be disabled.
VDDVR specification. For automotive grade models, the internal voltage regulator must not be used and this pin must be tied to V
DDINT
DDEXT
DDDDR
DDUSB
DDRTC
DDVR
DDMP
OUT
MP
12
0, VR
11
11
11
11
11
11
Table 41 on Page 73
OUT
1
through
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 49 on Page 74
for Driver Types.
Rev. A | Page 33 of 88 | October 2008
I/O
I
I
O
I
I
I
O
O
C
C
C
O
C
O
I
I
P
P
P
P
P
P
G
P
G
O
1
Function (First/Second/Third/Fourth)
Boot Mode Strap 0–3
JTAG Serial Data In
JTAG Serial Data Out
JTAG Reset (Pull low when unused.)
JTAG Mode Select
JTAG Clock
Emulation Output
External FET/BJT Drivers (Always connect together to reduce signal
impedance.)
RTC Crystal Output (Leave unconnected when unused.)
RTC Crystal Input (Pull high or low when unused.)
Clock/Crystal Input
Clock Output
Crystal Output
Buffered Oscillator Output
External Wakeup from Hibernate Output
Reset
Non-maskable Interrupt (Pull high when unused.)
Internal Power Supply
External Power Supply
External DDR1 Power Supply
External USB Power Supply
RTC Clock Supply
Internal Voltage Regulator Power Supply (Connect to V
when unused.)
Ground
MXVR PLL Power Supply (Connect to V
is not present.)
MXVR PLL Ground (Connect to GND when unused or when MXVR is not
present.)
Booting Modes on Page
19.
DDEXT
DDINT
. Otherwise it should be powered according to the
when unused or when MXVR
DDEXT
.
DDEXT
Driver
Type
C
C
B
C
A
2