adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 61

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Serial Peripheral Interface (SPI) Port—Master Timing
Table 40
Table 40. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
and
Figure 30
CPHA = 1
CPHA = 0
SPIxMISO
SPIxMISO
(INPUT)
(INPUT)
SPIxSELy
(OUTPUT)
(OUTPUT)
Data Input Valid to SPIxSCK Edge (Data Input Setup)
SPIxSCK Sampling Edge to Data Input Invalid
SPIxSELy Low to First SPIxSCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SPIxSCK Edge to SPIxSELy High
Sequential Transfer Delay
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
(OUTPUT)
SPIxMOSI
(CPOL = 0)
(CPOL = 1)
(OUTPUT)
(OUTPUT)
SPIxMOSI
SPIxSCK
SPIxSCK
describe SPI port master operations.
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
t
SSPIDM
t
SDSCIM
VALID
MSB
MSB
t
t
SPICHM
SPICLM
Figure 30. Serial Peripheral Interface (SPI) Port—Master Timing
VALID
t
MSB
HSPIDM
t
t
Rev. A | Page 61 of 88 | October 2008
MSB
SPICHM
SPICLM
t
HDSPIDM
t
HDSPIDM
t
DDSPIDM
t
t
SPICLK
t
DDSPIDM
SSPIDM
VALID
LSB
LSB
VALID
LSB
t
HDSM
LSB
t
HSPIDM
t
SPITDM
Min
9.0
–1.5
2t
2t
2t
4t
2t
2t
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
Max
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns