adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 62

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 41
Table 41. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
DSOE
DSDHI
DDSPID
HDSPID
HSPID
and
Figure 31
CPHA = 1
CPHA = 0
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SPIxSCK Edge to SPIxSS Not Asserted
Sequential Transfer Delay
SPIxSS Assertion to First SPIxSCK Edge
Data Input Valid to SPIxSCK Edge (Data Input Setup)
SPIxSCK Sampling Edge to Data Input Invalid
SPIxSS Assertion to Data Out Active
SPIxSS Deassertion to Data High Impedance
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
(CPOL = 1)
(CPOL = 0)
(OUTPUT)
SPIxMISO
(OUTPUT)
SPIxSCK
SPIxSCK
(INPUT)
(INPUT)
SPIxMISO
SPIxMOSI
SPIxMOSI
SPIxSS
(INPUT)
(INPUT)
(INPUT)
describe SPI port slave operations.
t
t
DSOE
DSOE
t
SDSCI
VALID
MSB
t
SSPID
Figure 31. Serial Peripheral Interface (SPI) Port—Slave Timing
t
MSB
t
t
DDSPID
SPICHS
SPICLS
VALID
MSB
Rev. A | Page 62 of 88 | October 2008
t
t
MSB
SPICLS
SPICHS
t
t
t
HSPID
HDSPID
HDSPID
t
HDSPID
t
DDSPID
t
SSPID
t
DDSPID
VALID
LSB
t
SPICLK
t
LSB
HDSPID
VALID
t
LSB
HSPID
LSB
t
HDS
t
DSDHI
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
t
SPITDS
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
DSDHI
–1.5
–1.5
Max
8
8
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns