adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 11

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

The memory DMA channels of the DMAC1 controller
(MDMA2 and MDMA3) can be optionally controlled by the
external DMA request input pins. When used in conjunction
with the External Bus Interface Unit (EBIU), this handshaked
memory DMA (HMDMA) scheme can be used to efficiently
exchange data with block-buffered or FIFO-style devices con-
nected externally. Users can select whether the DMA request
pins control the source or the destination side of the memory
DMA. It allows control of the number of data transfers for
memory DMA. The number of transfers per edge is program-
mable. This feature can be programmed to allow memory DMA
to have an increased priority on the external bus relative to the
core.
Host DMA Port Interface
The host DMA port (HOSTDP) facilitates a host device external
to the ADSP-BF54x Blackfin processors to be a DMA master
and transfer data back and forth. The host device always masters
the transactions, and the processor is always a DMA slave
device.
The HOSTDP is enabled through the peripheral access bus.
Once the port has been enabled, the transactions are controlled
by the external host. The external host programs standard DMA
configuration words in order to send/receive data to any valid
internal or external memory location. The host DMA port con-
troller includes the following features:
REAL-TIME CLOCK
The ADSP-BF54x Blackfin processors’ real-time clock (RTC)
provides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz
crystal external to the ADSP-BF54x Blackfin processors. The
RTC peripheral has dedicated power supply pins so that it can
remain powered up and clocked even when the rest of the pro-
cessor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and a 32,768-day counter.
• Allows an external master to configure DMA read/write
• Uses a flexible asynchronous memory protocol for its
• Allows an 8- or 16-bit external data interface to the host
• Supports half-duplex operation
• Supports little/big endian data transfers
• Acknowledge mode allows flow control on host
• Interrupt mode guarantees a burst of FIFO depth host
data transfers and read port status
external interface
device
transactions
transactions
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. A | Page 11 of 88 | October 2008
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed value
with one-second resolution. When the stopwatch is enabled and
the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the
ADSP-BF54x processors from sleep mode upon generation of
any RTC wakeup event. Additionally, an RTC wakeup event can
wake up the ADSP-BF54x processors from deep sleep mode,
and it can wake up the on-chip internal voltage regulator from
the hibernate state.
Connect RTC pins RTXI and RTXO with external components
as shown in
WATCHDOG TIMER
The ADSP-BF54x processors include a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system reliability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF54x processors’ peripher-
als. After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
watchdog timer control register.
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
C1
RTXI
Figure
Figure 4. External Components for RTC
4.
R1
X1
C2
RTXO