adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 16

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
The MXVR peripheral can wake up the ADSP-BF549 Blackfin
processor from sleep mode when a wakeup preamble is received
over the network or based on any other MXVR interrupt event.
Additionally, detection of network activity by the MXVR can be
used to wake up the ADSP-BF549 Blackfin processor from the
hibernate state. These features allow the ADSP-BF549 to oper-
ate in a low-power state when there is no network activity or
when data is not currently being received or transmitted by
the MXVR.
DYNAMIC POWER MANAGEMENT
The ADSP-BF54x Blackfin processors provide five operating
modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF54x Blackfin processors’ peripherals also
reduces power consumption. See
power settings for each mode.
Full-On Operating Mode
In the full-on mode, the PLL is enabled and is not bypassed,
providing the capability to run at the maximum operational fre-
quency. This is the power-up default execution state in which
maximum performance can be achieved. The processor core
and all enabled peripherals run at full speed.
Active Operating Mode
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
1.25V
330
R1
C1
0.047 F
2% PPS
600Z
0.01 F
1%
−
−
C2
330pF
2% PPS
Moderate Power Savings
Maximum Performance
24.576MHz
Table 5
0.1 F
VDDINT
GND
VDDMP
GNDMP
MXO
MXI
MLF_P
MLF_M
for a summary of the
ADSP-BF549
Rev. A | Page 16 of 88 | October 2008
PG11/MTXON
PC7/RSCLK0
PC3/TSCLK0
PH7/MRXON
PC1/MMCLK
PC5/MBCLK
PC2/DT0PRI
PC4/RFS0
Figure 5. MXVR MOST Connection
PH6/MRX
PH5/MTX
MFS
10k
33
33
33
27
5.0V
XN4114
The MXVR clock is provided through a dedicated external crys-
tal or crystal oscillator. The frequency of the external crystal or
crystal oscillator can be 256 Fs, 384 Fs, 512 Fs, or 1024 Fs for
Fs = 38 kHz, 44.1 kHz, or 48 kHz. If using a crystal to provide
the MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). For more informa-
tion, see the “Dynamic Power Management” chapter in the
ADSP-BF54x Blackfin Processor Hardware Reference. If dis-
abled, the PLL must be re-enabled before transitioning to the
full-on or sleep modes.
Table 5. Power Settings
Full On
Active
Sleep
Deep Sleep
Hibernate
600Z
600Z
0
Enabled
Enabled/
Disabled
Enabled
Disabled
Disabled
RXVCC
RXGND
TXVCC
TXGND
TX_DATA
RX_DATA
STATUS
L/RCLK
MCLK
BCLK
SDATA
AUDIO DAC
MOST FOT
No
Yes
−
−
−
Enabled
Enabled
Disabled
Disabled
Disabled
MOST
NETWORK
AUDIO
CHANNELS
Enabled
Enabled
Enabled
Disabled
Disabled
On
On
On
On
Off