adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 18

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
CLOCK SIGNALS
The ADSP-BF54x Blackfin processors can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF54x Blackfin processors
include an on-chip oscillator circuit, an external crystal may be
used. For fundamental frequency operation, use the circuit
shown in
microprocessor-grade crystal is connected across the CLKIN
and XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in
sine frequency.
The capacitor and resistor values shown in
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
100μF
2.7V TO 3.6V
INPUT VOLTAGE
RANGE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
+
Figure
LOW ESR
10μF
100nF
7. A parallel-resonant, fundamental frequency,
Figure 6. Voltage Regulator Circuit
Figure 7
(LOW-INDUCTANCE)
FDS9431A
V
fine tune phase and amplitude of the
DDVR
ZHCS1000
INDUCTANCE WIRE
SHORT AND LOW-
10μH
SET OF DECOUPLING
CAPACITORS
100μF
Figure 7
+
Rev. A | Page 18 of 88 | October 2008
are typical
V
V
VR
VR
GND
DDVR
DDINT
OUT
OUT
A third-overtone crystal can be used at frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in
ation is discussed in detail in an Application Note, Using Third
Overtone Crystals (EE-168).
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable 0.5× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 8×, but it can
be modified by a software instruction sequence. This sequence
is managed by the bfrom_SysControl() function in the on-chip
ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
Whereas the maximum allowed CCLK and SCLK rates depend
on the applied voltages V
permitted to run up to the frequency specified by the part’s
speed grade.
The CLKOUT pin reflects the SCLK frequency to the off-chip
world. It functions as a reference for many timing specifications.
While inactive by default, it can be enabled using the
EBIU_AMGCTL register.
CLKOUT
CLKBUF
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure
Figure 7. External Crystal Connections
7. A design procedure for third-overtone oper-
EN
EN
DDINT
Figure 8 on Page
CLKIN
BLACKFIN
18 pF*
and V
330 *
TO PLL CIRCUITRY
DDEXT
XTAL
18 pF*
, the VCO is always
FOR OVERTONE
OPERATION ONLY:
19, the core clock