adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 14

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
PORTS
Because of their rich set of peripherals, the ADSP-BF54x
Blackfin processors group the many peripheral signals to ten
ports—referred to as Port A to Port J. Most ports contain 16
pins, though some have less. Many of the associated pins are
shared by multiple signals. The ports function as multiplexer
controls. Every port has its own set of memory-mapped regis-
ters to control port muxing and GPIO functionality.
General-Purpose I/O (GPIO)
Every pin in Port A to Port J can function as a GPIO pin, result-
ing in a GPIO pin count of 154. While it is unlikely that all
GPIOs will be used in an application, as all pins have multiple
functions, the richness of GPIO functionality guarantees unre-
strictive pin usage. Every pin that is not used by any function
can be configured in GPIO mode on an individual basis.
After reset, all pins are in GPIO mode by default. Since neither
GPIO output nor input drivers are active by default, unused
pins can be left unconnected. GPIO data and direction control
registers provide flexible write-one-to-set and write-one-to-
clear mechanisms so that independent software threads do not
need to protect against each other because of expensive read-
modify-write operations when accessing the same port.
Pin Interrupts
Every port pin on ADSP-BF54x Blackfin processors can request
interrupts in either an edge-sensitive or a level-sensitive manner
with programmable polarity. Interrupt functionality is decou-
pled from GPIO operation. Four system-level interrupt
channels (PINT0, PINT1, PINT2 and PINT3) are reserved for
this purpose. Each of these interrupt channels can manage up to
32 interrupt pins. The assignment from pin to interrupt is not
performed on a pin by pin basis. Rather, groups of eight pins
(half ports) can be flexibly assigned to interrupt channels.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enables half-port assignment and
interrupt management. This not only includes masking, identi-
fication, and clearing of requests, it also enables access to the
respective pin states and use of the interrupt latches regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
PIXEL COMPOSITOR (PIXC)
The pixel compositor (PIXC) provides image overlays with
transparent-color support, alpha blending, and color space con-
version capabilities for output to TFT-LCDs and NTSC/PAL
video encoders. It provides all of the control to allow two data
streams from two separate data buffers to be combined,
blended, and converted into appropriate forms for both LCD
panels and digital video outputs. The main image buffer pro-
vides the basic background image, which is presented in the
data stream. The overlay image buffer allows the user to add
multiple foreground text, graphics, or video objects on top of
the main image or video data stream.
Rev. A | Page 14 of 88 | October 2008
ENHANCED PARALLEL PERIPHERAL INTERFACE
(EPPI)
The ADSP-BF54x Blackfin processors provide up to three
enhanced parallel peripheral interfaces (EPPIs), supporting data
widths up to 24 bits. The EPPI supports direct connection to
TFT LCD panels, parallel analog-to-digital and digital-to-ana-
log converters, video encoders and decoders, image sensor
modules and other general purpose peripherals.
The following features are supported in the EPPI module.
USB ON-THE-GO DUAL-ROLE DEVICE
CONTROLLER
The USB OTG dual-role device controller (USBDRC) provides
a low-cost connectivity solution for consumer mobile devices
such as cell phones, digital still cameras, and MP3 players,
allowing these devices to transfer data using a point-to-point
• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,
• Bidirectional and half-duplex port.
• Clock can be provided externally or can be generated
• Various framed and non-framed operating modes. Frame
• Various general purpose modes with zero to three frame
• ITU-656 status word error detection and correction for
• ITU-656 preamble and status word decode.
• Three different modes for ITU-656 receive modes: active
• Horizontal and vertical windowing for GP 2 and 3 frame
• Optional packing and unpacking of data to/from 32 bits
• Optional sign extension or zero fill for receive modes.
• During receive modes, alternate even or odd data samples
• Programmable clipping of data values for 8-bit transmit
• RGB888 can be converted to RGB666 or RGB565 for trans-
• Various de-interleaving/interleaving modes for receiv-
• FIFO watermarks and urgent DMA features.
• Clock gating by an external device asserting the clock gat-
• Configurable LCD data enable (DEN) output available on
16 bits, 18 bits, and 24 bits per clock.
internally.
syncs can be generated internally or can be supplied by an
external device.
syncs for both receive and transmit directions.
ITU-656 receive modes.
video only, vertical blanking only, and entire field mode.
sync modes.
from/to 8, 16 and 24 bits. If packing/unpacking is enabled,
endianness can be changed to change the order of pack-
ing/unpacking of bytes/words.
can be filtered out.
modes.
mit modes.
ing/transmitting 4:2:2 YCrCb data.
ing control signal.
Frame Sync 3.