adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 21

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

NAND flash boot supports the following features:
Small page NAND flash devices must have a 512-byte page
size, 32 pages per block, a 16-byte spare area size and a bus
configuration of 8 bits. By default, all read requests from
the NAND flash are followed by 4 address cycles. If the
NAND flash device requires only 3 address cycles, then the
device must be capable of ignoring the additional
address cycle.
The small page NAND flash device must comply with the
following command set:
Reset: 0xFF
Read lower half of page: 0x00
Read upper half of page: 0x01
Read spare area: 0x50
For large page NAND flash devices, the 4-byte electronic
signature is read in order to configure the kernel for boot-
ing. This allows support for multiple large page devices.
Byte 4 of the electronic signature must comply with the
specifications in
Any configuration from
the command set listed below is directly supported by the
boot kernel. There are no restrictions on the page size or
block size as imposed by the small page boot kernel.
Large page devices must support the following command
set:
Reset: 0xFF
Read Electronic Signature: 0x90
Read: 0x00, 0x30 (confirm command)
Large page devices must not support or react to NAND
flash command 0x50. This is a small page NAND flash
command used for device auto detection.
By default, the boot kernel will always issue 5 address
cycles; therefore, if a large page device requires only 4
cycles, the device must be capable of ignoring the addi-
tional address cycle.
• Device auto detection
• Error detection & correction for maximum reliability
• No boot stream size limitation
• Peripheral DMA via channel 22, providing efficient
• Software-configurable boot mode for booting from
• Software-configurable boot mode for booting from
• Configurable timing via OTP memory
transfer of all data (excluding the ECC parity data)
boot streams expanding multiple blocks, including
bad blocks
multiple copies of the boot stream allowing for han-
dling of bad blocks and uncorrectable errors
Table
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
10.
Table 10
that also complies with
Rev. A | Page 21 of 88 | October 2008
Table 10. Byte 4 Electronic Signature Specification
• Boot from OTP memory (BMODE=0xB)—This provides a
• Boot from 16-bit host DMA (BMODE=0xE)—In this
16-bit NAND flash memory devices must only support the
issuing of command and address cycles via the lower 8 bits
of the data bus. Devices that make use of the full 16-bit bus
for command and address cycles are not supported.
standalone booting method. The boot stream is loaded
from on-chip OTP memory. By default, the boot stream is
expected to start from OTP page 0x40 and can occupy all
public OTP memory up to page 0xDF (2560 bytes). Since
the start page is programmable, the maximum size of the
boot stream can be extended to 3072 bytes.
mode, the host DMA port is configured in 16-bit Acknowl-
edge mode with little endian data format. Unlike other
modes, the host is responsible for interpreting the boot
stream. It writes data blocks individually into the Host
DMA port. Before configuring the DMA settings for each
block, the host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the Host DMA Port. After completing the
configuration, the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host's responsibility to ensure valid code has been placed at
this address. The routine at address 0xFFA0 0000 can be a
simple initialization routine to configure internal
resources, such as the SDRAM controller, which then
Page Size
(excluding spare
area)
Spare Area Size
Block Size
(excluding spare
area)
Bus width
Not Used for
configuration
D1:D0
D2
D5:4
D6
D3, D7
00
01
10
11
0
1
00
01
10
11
0
1
1K Bytes
2K Bytes
4K Bytes
8K Bytes
8 Bytes/512 Bytes
16 Bytes/512 Bytes
64K Bytes
128K Bytes
256K Bytes
512K Bytes
x8
x16