adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 37

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Total power dissipation has two components:
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity.
current dissipation for internal circuitry (V
fies static power dissipation as a function of voltage (V
temperature (see
Table 16. Static Current (mA)
1
2
Table 17. Activity Scaling Factors
1
T
-40
0
25
45
55
70
85
100
105
Values are guaranteed maximum I
Valid temperature and voltage ranges are model-specific. See
I
I
I
I
I
I
I
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
DD-PEAK
DD-HIGH
DD-TYP
DD-APP
DD-NOP
DD-IDLE
DDINT
(EE-297). The power vector information also applies to the ADSP-
BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 processors.
J
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
(°C)
Power Vector
2
0.90 V
19.7
45.2
80.0
124.2
154.6
209.8
281.8
366.5
403.8
Electrical Characteristics on Page 36
Table
0.95 V
22.1
49.9
87.5
134.8
167.2
225.6
301.3
390.5
428.3
16), and I
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDDEEPSLEEP
Activity Scaling Factor (ASF)
1.29
1.24
1.00
0.87
0.74
0.47
1
1.00 V
24.8
55.2
96.2
147.1
181.7
243.9
323.5
419.4
459.5
DDINT
.
1
specifies the total power
DDINT
27.9
61.3
160.7
197.7
264.1
350.2
452.1
494.3
1.05 V
105.8
). I
DDDEEPSLEEP
Operating Conditions on Page
Rev. A | Page 37 of 88 | October 2008
shows the
DDINT
1.10 V
31.4
67.9
116.4
175.3
214.9
285.8
378.5
486.9
531.7
speci-
) and
Voltage (V
1.15 V
35.4
75.3
127.9
191.2
233.8
309.4
408.9
524.4
571.9
specification for the listed test conditions, including the
dynamic component as a function of voltage (V
quency
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories
Frequency and V
this part. The second part is due to transistor switching in the
system clock (SCLK) domain and is included in the I
fication equation.
34.
DDINT
1.20 V
39.9
83.5
140.4
208.6
254.2
334.8
442.1
564.8
614.9
)
2
(Table
(Table
18).
DDINT
1.25 V
45.0
92.6
154.1
227.3
276.1
363.5
477.9
608.2
661.5
17). The ASF is combined with the CCLK
dependent data in
1.30 V
50.6
102.6
169.2
247.6
299.7
394.3
516.5
654.8
711.1
Table 16
1.35 V
57.0
113.6
185.4
269.6
325.9
427.7
557.5
704.7
763.9
DDINT
to calculate
) and fre-
DDINT
1.40 V
64.0
125.8
203.3
293.6
354.6
463.9
602.0
758.5
821.6
speci-